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Put logic devices into scopes.

This commit is contained in:
steve 2000-10-07 19:45:42 +00:00
parent 6f69773c57
commit 76e2c509d7
13 changed files with 275 additions and 154 deletions
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24
cprop.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: cprop.cc,v 1.16 2000/10/06 21:26:34 steve Exp $" #ident "$Id: cprop.cc,v 1.17 2000/10/07 19:45:42 steve Exp $"
#endif #endif
# include "netlist.h" # include "netlist.h"
@ -108,14 +108,15 @@ void cprop_functor::lpm_add_sub(Design*des, NetAddSub*obj)
if (obj->width() == 1) { if (obj->width() == 1) {
NetLogic*tmp; NetLogic*tmp;
if (obj->pin_Cout().is_linked()) { if (obj->pin_Cout().is_linked()) {
tmp = new NetLogic(des->local_symbol(obj->name()), 3, tmp = new NetLogic(obj->scope(),
NetLogic::AND); des->local_symbol(obj->name()), 3,
NetLogic::AND);
connect(tmp->pin(0), obj->pin_Cout()); connect(tmp->pin(0), obj->pin_Cout());
connect(tmp->pin(1), obj->pin_DataA(0)); connect(tmp->pin(1), obj->pin_DataA(0));
connect(tmp->pin(2), obj->pin_DataB(0)); connect(tmp->pin(2), obj->pin_DataB(0));
des->add_node(tmp); des->add_node(tmp);
} }
tmp = new NetLogic(obj->name(), 3, NetLogic::XOR); tmp = new NetLogic(obj->scope(), obj->name(), 3, NetLogic::XOR);
connect(tmp->pin(0), obj->pin_Result(0)); connect(tmp->pin(0), obj->pin_Result(0));
connect(tmp->pin(1), obj->pin_DataA(0)); connect(tmp->pin(1), obj->pin_DataA(0));
connect(tmp->pin(2), obj->pin_DataB(0)); connect(tmp->pin(2), obj->pin_DataB(0));
@ -246,7 +247,8 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
} }
if (top == 2) { if (top == 2) {
NetLogic*tmp = new NetLogic(obj->name(), top, NetLogic*tmp = new NetLogic(obj->scope(),
obj->name(), top,
NetLogic::BUF); NetLogic::BUF);
des->add_node(tmp); des->add_node(tmp);
tmp->pin(0).drive0(obj->pin(0).drive0()); tmp->pin(0).drive0(obj->pin(0).drive0());
@ -259,7 +261,8 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
} }
if (top < obj->pin_count()) { if (top < obj->pin_count()) {
NetLogic*tmp = new NetLogic(obj->name(), top, NetLogic*tmp = new NetLogic(obj->scope(),
obj->name(), top,
NetLogic::XOR); NetLogic::XOR);
des->add_node(tmp); des->add_node(tmp);
tmp->pin(0).drive0(obj->pin(0).drive0()); tmp->pin(0).drive0(obj->pin(0).drive0());
@ -307,7 +310,8 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
if (flag) { if (flag) {
for (unsigned idx = 0 ; idx < obj->width() ; idx += 1) { for (unsigned idx = 0 ; idx < obj->width() ; idx += 1) {
NetLogic*tmp = new NetLogic(des->local_symbol(obj->name()), NetLogic*tmp = new NetLogic(obj->scope(),
des->local_symbol(obj->name()),
3, NetLogic::BUFIF1); 3, NetLogic::BUFIF1);
connect(obj->pin_Result(idx), tmp->pin(0)); connect(obj->pin_Result(idx), tmp->pin(0));
@ -338,7 +342,8 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
if (flag) { if (flag) {
for (unsigned idx = 0 ; idx < obj->width() ; idx += 1) { for (unsigned idx = 0 ; idx < obj->width() ; idx += 1) {
NetLogic*tmp = new NetLogic(des->local_symbol(obj->name()), NetLogic*tmp = new NetLogic(obj->scope(),
des->local_symbol(obj->name()),
3, NetLogic::BUFIF0); 3, NetLogic::BUFIF0);
connect(obj->pin_Result(idx), tmp->pin(0)); connect(obj->pin_Result(idx), tmp->pin(0));
@ -428,6 +433,9 @@ void cprop(Design*des)
/* /*
* $Log: cprop.cc,v $ * $Log: cprop.cc,v $
* Revision 1.17 2000/10/07 19:45:42 steve
* Put logic devices into scopes.
*
* Revision 1.16 2000/10/06 21:26:34 steve * Revision 1.16 2000/10/06 21:26:34 steve
* Eliminate zero inputs to xor. * Eliminate zero inputs to xor.
* *

9
design_dump.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: design_dump.cc,v 1.99 2000/10/06 23:46:50 steve Exp $" #ident "$Id: design_dump.cc,v 1.100 2000/10/07 19:45:42 steve Exp $"
#endif #endif
/* /*
@ -228,7 +228,8 @@ void NetAssign_::dump_node(ostream&o, unsigned ind) const
void NetBUFZ::dump_node(ostream&o, unsigned ind) const void NetBUFZ::dump_node(ostream&o, unsigned ind) const
{ {
o << setw(ind) << "" << "NetBUFZ: " << name() << endl; o << setw(ind) << "" << "NetBUFZ: " << name()
<< " scope=" << (scope()? scope()->name() : "") << endl;
dump_node_pins(o, ind+4); dump_node_pins(o, ind+4);
} }
@ -291,6 +292,7 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
} }
o << " #(" << rise_time() o << " #(" << rise_time()
<< "," << fall_time() << "," << decay_time() << ") " << name() << "," << fall_time() << "," << decay_time() << ") " << name()
<< " scope=" << (scope()? scope()->name() : "")
<< endl; << endl;
dump_node_pins(o, ind+4); dump_node_pins(o, ind+4);
@ -971,6 +973,9 @@ void Design::dump(ostream&o) const
/* /*
* $Log: design_dump.cc,v $ * $Log: design_dump.cc,v $
* Revision 1.100 2000/10/07 19:45:42 steve
* Put logic devices into scopes.
*
* Revision 1.99 2000/10/06 23:46:50 steve * Revision 1.99 2000/10/06 23:46:50 steve
* ivl_target updates, including more complete * ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced * handling of ivl_nexus_t objects. Much reduced

81
elab_net.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: elab_net.cc,v 1.48 2000/09/26 05:05:58 steve Exp $" #ident "$Id: elab_net.cc,v 1.49 2000/10/07 19:45:42 steve Exp $"
#endif #endif
# include "PExpr.h" # include "PExpr.h"
@ -264,8 +264,8 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, const string&path,
switch (op_) { switch (op_) {
case '^': // XOR case '^': // XOR
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) { for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
NetLogic*gate = new NetLogic(des->local_symbol(path), 3, NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
NetLogic::XOR); 3, NetLogic::XOR);
connect(gate->pin(1), lsig->pin(idx)); connect(gate->pin(1), lsig->pin(idx));
connect(gate->pin(2), rsig->pin(idx)); connect(gate->pin(2), rsig->pin(idx));
connect(gate->pin(0), osig->pin(idx)); connect(gate->pin(0), osig->pin(idx));
@ -278,8 +278,8 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, const string&path,
case 'X': // XNOR case 'X': // XNOR
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) { for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
NetLogic*gate = new NetLogic(des->local_symbol(path), 3, NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
NetLogic::XNOR); 3, NetLogic::XNOR);
connect(gate->pin(1), lsig->pin(idx)); connect(gate->pin(1), lsig->pin(idx));
connect(gate->pin(2), rsig->pin(idx)); connect(gate->pin(2), rsig->pin(idx));
connect(gate->pin(0), osig->pin(idx)); connect(gate->pin(0), osig->pin(idx));
@ -292,8 +292,8 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, const string&path,
case '&': // AND case '&': // AND
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) { for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
NetLogic*gate = new NetLogic(des->local_symbol(path), 3, NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
NetLogic::AND); 3, NetLogic::AND);
connect(gate->pin(1), lsig->pin(idx)); connect(gate->pin(1), lsig->pin(idx));
connect(gate->pin(2), rsig->pin(idx)); connect(gate->pin(2), rsig->pin(idx));
connect(gate->pin(0), osig->pin(idx)); connect(gate->pin(0), osig->pin(idx));
@ -306,7 +306,7 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, const string&path,
case '|': // Bitwise OR case '|': // Bitwise OR
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) { for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
NetLogic*gate = new NetLogic(des->local_symbol(path), NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
3, NetLogic::OR); 3, NetLogic::OR);
connect(gate->pin(1), lsig->pin(idx)); connect(gate->pin(1), lsig->pin(idx));
connect(gate->pin(2), rsig->pin(idx)); connect(gate->pin(2), rsig->pin(idx));
@ -412,7 +412,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
case 'E': // Case equals (===) case 'E': // Case equals (===)
// The comparison generates gates to bitwise compare // The comparison generates gates to bitwise compare
// each pair, and AND all the comparison results. // each pair, and AND all the comparison results.
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
1+lsig->pin_count(), 1+lsig->pin_count(),
NetLogic::AND); NetLogic::AND);
connect(gate->pin(0), osig->pin(0)); connect(gate->pin(0), osig->pin(0));
@ -446,7 +446,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
/* Handle the special case of single bit compare with a /* Handle the special case of single bit compare with a
single XNOR gate. This is easy and direct. */ single XNOR gate. This is easy and direct. */
if (dwidth == 1) { if (dwidth == 1) {
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
3, NetLogic::XNOR); 3, NetLogic::XNOR);
connect(gate->pin(0), osig->pin(0)); connect(gate->pin(0), osig->pin(0));
connect(gate->pin(1), lsig->pin(0)); connect(gate->pin(1), lsig->pin(0));
@ -455,11 +455,11 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
} }
/* Oh well, do the general case. */ /* Oh well, do the general case. */
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
1+dwidth,NetLogic::AND); 1+dwidth,NetLogic::AND);
connect(gate->pin(0), osig->pin(0)); connect(gate->pin(0), osig->pin(0));
for (unsigned idx = 0 ; idx < dwidth ; idx += 1) { for (unsigned idx = 0 ; idx < dwidth ; idx += 1) {
NetLogic*cmp = new NetLogic(des->local_symbol(path), NetLogic*cmp = new NetLogic(scope, des->local_symbol(path),
3, NetLogic::XNOR); 3, NetLogic::XNOR);
if (idx < lsig->pin_count()) if (idx < lsig->pin_count())
connect(cmp->pin(1), lsig->pin(idx)); connect(cmp->pin(1), lsig->pin(idx));
@ -487,7 +487,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
/* Handle the special case of single bit compare with a /* Handle the special case of single bit compare with a
single XOR gate. This is easy and direct. */ single XOR gate. This is easy and direct. */
if (dwidth == 1) { if (dwidth == 1) {
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
3, NetLogic::XOR); 3, NetLogic::XOR);
connect(gate->pin(0), osig->pin(0)); connect(gate->pin(0), osig->pin(0));
connect(gate->pin(1), lsig->pin(0)); connect(gate->pin(1), lsig->pin(0));
@ -495,12 +495,12 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
break; break;
} }
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
1+dwidth, NetLogic::OR); 1+dwidth, NetLogic::OR);
connect(gate->pin(0), osig->pin(0)); connect(gate->pin(0), osig->pin(0));
for (unsigned idx = 0 ; idx < dwidth ; idx += 1) { for (unsigned idx = 0 ; idx < dwidth ; idx += 1) {
NetLogic*cmp = new NetLogic(des->local_symbol(path), 3, NetLogic*cmp = new NetLogic(scope, des->local_symbol(path),
NetLogic::XOR); 3, NetLogic::XOR);
if (idx < lsig->pin_count()) if (idx < lsig->pin_count())
connect(cmp->pin(1), lsig->pin(idx)); connect(cmp->pin(1), lsig->pin(idx));
else else
@ -665,10 +665,12 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, const string&path,
NetLogic*gate_t; NetLogic*gate_t;
switch (op_) { switch (op_) {
case 'a': case 'a':
gate = new NetLogic(des->local_symbol(path), 3, NetLogic::AND); gate = new NetLogic(scope, des->local_symbol(path),
3, NetLogic::AND);
break; break;
case 'o': case 'o':
gate = new NetLogic(des->local_symbol(path), 3, NetLogic::OR); gate = new NetLogic(scope, des->local_symbol(path),
3, NetLogic::OR);
break; break;
default: default:
assert(0); assert(0);
@ -679,7 +681,7 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, const string&path,
// The first OR gate returns 1 if the left value is true... // The first OR gate returns 1 if the left value is true...
if (lsig->pin_count() > 1) { if (lsig->pin_count() > 1) {
gate_t = new NetLogic(des->local_symbol(path), gate_t = new NetLogic(scope, des->local_symbol(path),
1+lsig->pin_count(), NetLogic::OR); 1+lsig->pin_count(), NetLogic::OR);
for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1)
connect(gate_t->pin(idx+1), lsig->pin(idx)); connect(gate_t->pin(idx+1), lsig->pin(idx));
@ -699,7 +701,7 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, const string&path,
// The second OR gate returns 1 if the right value is true... // The second OR gate returns 1 if the right value is true...
if (rsig->pin_count() > 1) { if (rsig->pin_count() > 1) {
gate_t = new NetLogic(des->local_symbol(path), gate_t = new NetLogic(scope, des->local_symbol(path),
1+rsig->pin_count(), NetLogic::OR); 1+rsig->pin_count(), NetLogic::OR);
for (unsigned idx = 0 ; idx < rsig->pin_count() ; idx += 1) for (unsigned idx = 0 ; idx < rsig->pin_count() ; idx += 1)
connect(gate_t->pin(idx+1), rsig->pin(idx)); connect(gate_t->pin(idx+1), rsig->pin(idx));
@ -1536,7 +1538,7 @@ NetNet* PETernary::elaborate_net(Design*des, const string&path,
by connecting an OR gate to calculate the truth value of by connecting an OR gate to calculate the truth value of
the result. In the end, the result needs to be a single bit. */ the result. In the end, the result needs to be a single bit. */
if (expr_sig->pin_count() > 1) { if (expr_sig->pin_count() > 1) {
NetLogic*log = new NetLogic(des->local_symbol(path), NetLogic*log = new NetLogic(scope, des->local_symbol(path),
expr_sig->pin_count()+1, expr_sig->pin_count()+1,
NetLogic::OR); NetLogic::OR);
for (unsigned idx = 0; idx < expr_sig->pin_count(); idx += 1) for (unsigned idx = 0; idx < expr_sig->pin_count(); idx += 1)
@ -1642,8 +1644,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
sub_sig->pin_count()); sub_sig->pin_count());
sig->local_flag(true); sig->local_flag(true);
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) { for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) {
gate = new NetLogic(des->local_symbol(path), 2, gate = new NetLogic(scope, des->local_symbol(path),
NetLogic::NOT); 2, NetLogic::NOT);
connect(gate->pin(1), sub_sig->pin(idx)); connect(gate->pin(1), sub_sig->pin(idx));
connect(gate->pin(0), sig->pin(idx)); connect(gate->pin(0), sig->pin(idx));
des->add_node(gate); des->add_node(gate);
@ -1657,9 +1659,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
case '!': // Reduction NOT case '!': // Reduction NOT
sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE); sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
sig->local_flag(true); sig->local_flag(true);
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
1+sub_sig->pin_count(), 1+sub_sig->pin_count(), NetLogic::NOR);
NetLogic::NOR);
connect(gate->pin(0), sig->pin(0)); connect(gate->pin(0), sig->pin(0));
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
connect(gate->pin(idx+1), sub_sig->pin(idx)); connect(gate->pin(idx+1), sub_sig->pin(idx));
@ -1673,9 +1674,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
case '&': // Reduction AND case '&': // Reduction AND
sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE); sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
sig->local_flag(true); sig->local_flag(true);
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
1+sub_sig->pin_count(), 1+sub_sig->pin_count(), NetLogic::AND);
NetLogic::AND);
connect(gate->pin(0), sig->pin(0)); connect(gate->pin(0), sig->pin(0));
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
connect(gate->pin(idx+1), sub_sig->pin(idx)); connect(gate->pin(idx+1), sub_sig->pin(idx));
@ -1689,9 +1689,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
case '|': // Reduction OR case '|': // Reduction OR
sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE); sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
sig->local_flag(true); sig->local_flag(true);
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
1+sub_sig->pin_count(), 1+sub_sig->pin_count(), NetLogic::OR);
NetLogic::OR);
connect(gate->pin(0), sig->pin(0)); connect(gate->pin(0), sig->pin(0));
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
connect(gate->pin(idx+1), sub_sig->pin(idx)); connect(gate->pin(idx+1), sub_sig->pin(idx));
@ -1705,9 +1704,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
case '^': // Reduction XOR case '^': // Reduction XOR
sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE); sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
sig->local_flag(true); sig->local_flag(true);
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
1+sub_sig->pin_count(), 1+sub_sig->pin_count(), NetLogic::XOR);
NetLogic::XOR);
connect(gate->pin(0), sig->pin(0)); connect(gate->pin(0), sig->pin(0));
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
connect(gate->pin(idx+1), sub_sig->pin(idx)); connect(gate->pin(idx+1), sub_sig->pin(idx));
@ -1721,9 +1719,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
case 'A': // Reduction NAND (~&) case 'A': // Reduction NAND (~&)
sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE); sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
sig->local_flag(true); sig->local_flag(true);
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
1+sub_sig->pin_count(), 1+sub_sig->pin_count(), NetLogic::NAND);
NetLogic::NAND);
connect(gate->pin(0), sig->pin(0)); connect(gate->pin(0), sig->pin(0));
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
connect(gate->pin(idx+1), sub_sig->pin(idx)); connect(gate->pin(idx+1), sub_sig->pin(idx));
@ -1738,9 +1735,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
case 'X': // Reduction XNOR (~^) case 'X': // Reduction XNOR (~^)
sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE); sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
sig->local_flag(true); sig->local_flag(true);
gate = new NetLogic(des->local_symbol(path), gate = new NetLogic(scope, des->local_symbol(path),
1+sub_sig->pin_count(), 1+sub_sig->pin_count(), NetLogic::XNOR);
NetLogic::XNOR);
connect(gate->pin(0), sig->pin(0)); connect(gate->pin(0), sig->pin(0));
for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1) for (unsigned idx = 0 ; idx < sub_sig->pin_count() ; idx += 1)
connect(gate->pin(idx+1), sub_sig->pin(idx)); connect(gate->pin(idx+1), sub_sig->pin(idx));
@ -1764,6 +1760,9 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
/* /*
* $Log: elab_net.cc,v $ * $Log: elab_net.cc,v $
* Revision 1.49 2000/10/07 19:45:42 steve
* Put logic devices into scopes.
*
* Revision 1.48 2000/09/26 05:05:58 steve * Revision 1.48 2000/09/26 05:05:58 steve
* Detect indefinite widths where definite widths are required. * Detect indefinite widths where definite widths are required.
* *

44
elaborate.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: elaborate.cc,v 1.192 2000/09/29 22:58:57 steve Exp $" #ident "$Id: elaborate.cc,v 1.193 2000/10/07 19:45:42 steve Exp $"
#endif #endif
/* /*
@ -73,6 +73,9 @@ void PGate::elaborate(Design*des, const string&path) const
*/ */
void PGAssign::elaborate(Design*des, const string&path) const void PGAssign::elaborate(Design*des, const string&path) const
{ {
NetScope*scope = des->find_scope(path);
assert(scope);
unsigned long rise_time, fall_time, decay_time; unsigned long rise_time, fall_time, decay_time;
eval_delays(des, path, rise_time, fall_time, decay_time); eval_delays(des, path, rise_time, fall_time, decay_time);
@ -132,7 +135,8 @@ void PGAssign::elaborate(Design*des, const string&path) const
} else { } else {
unsigned idx; unsigned idx;
for (idx = 0 ; idx < cnt ; idx += 1) { for (idx = 0 ; idx < cnt ; idx += 1) {
NetBUFZ*dev = new NetBUFZ(des->local_symbol(path)); NetBUFZ*dev = new NetBUFZ(scope,
des->local_symbol(path));
connect(lval->pin(idx), dev->pin(0)); connect(lval->pin(idx), dev->pin(0));
connect(rid->pin(idx), dev->pin(1)); connect(rid->pin(idx), dev->pin(1));
dev->pin(0).drive0(drive0); dev->pin(0).drive0(drive0);
@ -198,6 +202,9 @@ void PGBuiltin::elaborate(Design*des, const string&path) const
unsigned count = 1; unsigned count = 1;
unsigned low = 0, high = 0; unsigned low = 0, high = 0;
string name = get_name(); string name = get_name();
NetScope*scope = des->find_scope(path);
if (name == "") if (name == "")
name = des->local_symbol(path); name = des->local_symbol(path);
else else
@ -270,34 +277,44 @@ void PGBuiltin::elaborate(Design*des, const string&path) const
switch (type()) { switch (type()) {
case AND: case AND:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::AND); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::AND);
break; break;
case BUF: case BUF:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUF); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::BUF);
break; break;
case BUFIF0: case BUFIF0:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUFIF0); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::BUFIF0);
break; break;
case BUFIF1: case BUFIF1:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUFIF1); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::BUFIF1);
break; break;
case NAND: case NAND:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NAND); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NAND);
break; break;
case NOR: case NOR:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NOR); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NOR);
break; break;
case NOT: case NOT:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NOT); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::NOT);
break; break;
case OR: case OR:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::OR); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::OR);
break; break;
case XNOR: case XNOR:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::XNOR); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::XNOR);
break; break;
case XOR: case XOR:
cur[idx] = new NetLogic(inm, pin_count(), NetLogic::XOR); cur[idx] = new NetLogic(scope, inm, pin_count(),
NetLogic::XOR);
break; break;
default: default:
cerr << get_line() << ": internal error: unhandled " cerr << get_line() << ": internal error: unhandled "
@ -2265,6 +2282,9 @@ Design* elaborate(const map<string,Module*>&modules,
/* /*
* $Log: elaborate.cc,v $ * $Log: elaborate.cc,v $
* Revision 1.193 2000/10/07 19:45:42 steve
* Put logic devices into scopes.
*
* Revision 1.192 2000/09/29 22:58:57 steve * Revision 1.192 2000/09/29 22:58:57 steve
* Do not put noop statements into blocks. * Do not put noop statements into blocks.
* *

42
expr_synth.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: expr_synth.cc,v 1.14 2000/05/02 00:58:12 steve Exp $" #ident "$Id: expr_synth.cc,v 1.15 2000/10/07 19:45:43 steve Exp $"
#endif #endif
# include "netlist.h" # include "netlist.h"
@ -76,12 +76,15 @@ NetNet* NetEBAdd::synthesize(Design*des)
*/ */
NetNet* NetEBBits::synthesize(Design*des) NetNet* NetEBBits::synthesize(Design*des)
{ {
string path = des->local_symbol("SYNTH");
NetNet*lsig = left_->synthesize(des); NetNet*lsig = left_->synthesize(des);
NetNet*rsig = right_->synthesize(des); NetNet*rsig = right_->synthesize(des);
NetScope*scope = lsig->scope();
assert(scope);
string path = des->local_symbol(scope->name());
assert(lsig->pin_count() == rsig->pin_count()); assert(lsig->pin_count() == rsig->pin_count());
NetNet*osig = new NetNet(lsig->scope(), path, NetNet::IMPLICIT, NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT,
lsig->pin_count()); lsig->pin_count());
osig->local_flag(true); osig->local_flag(true);
@ -91,19 +94,19 @@ NetNet* NetEBBits::synthesize(Design*des)
switch (op()) { switch (op()) {
case '&': case '&':
gate = new NetLogic(oname, 3, NetLogic::AND); gate = new NetLogic(scope, oname, 3, NetLogic::AND);
break; break;
case '|': case '|':
gate = new NetLogic(oname, 3, NetLogic::OR); gate = new NetLogic(scope, oname, 3, NetLogic::OR);
break; break;
case '^': case '^':
gate = new NetLogic(oname, 3, NetLogic::XOR); gate = new NetLogic(scope, oname, 3, NetLogic::XOR);
break; break;
case 'O': case 'O':
gate = new NetLogic(oname, 3, NetLogic::NOR); gate = new NetLogic(scope, oname, 3, NetLogic::NOR);
break; break;
case 'X': case 'X':
gate = new NetLogic(oname, 3, NetLogic::XNOR); gate = new NetLogic(scope, oname, 3, NetLogic::XNOR);
break; break;
default: default:
assert(0); assert(0);
@ -121,21 +124,24 @@ NetNet* NetEBBits::synthesize(Design*des)
NetNet* NetEBComp::synthesize(Design*des) NetNet* NetEBComp::synthesize(Design*des)
{ {
string path = des->local_symbol("SYNTH");
NetNet*lsig = left_->synthesize(des); NetNet*lsig = left_->synthesize(des);
NetNet*rsig = right_->synthesize(des); NetNet*rsig = right_->synthesize(des);
NetScope*scope = lsig->scope();
assert(scope);
string path = des->local_symbol(scope->name());
unsigned width = lsig->pin_count(); unsigned width = lsig->pin_count();
if (rsig->pin_count() > lsig->pin_count()) if (rsig->pin_count() > lsig->pin_count())
width = rsig->pin_count(); width = rsig->pin_count();
NetNet*osig = new NetNet(lsig->scope(), path, NetNet::IMPLICIT, 1); NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT, 1);
osig->local_flag(true); osig->local_flag(true);
/* Handle the special case of a single bit equality /* Handle the special case of a single bit equality
operation. Make an XNOR gate instead of a comparator. */ operation. Make an XNOR gate instead of a comparator. */
if ((width == 1) && ((op_ == 'e') || (op_ == 'E'))) { if ((width == 1) && ((op_ == 'e') || (op_ == 'E'))) {
NetLogic*gate = new NetLogic(des->local_symbol(path), NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
3, NetLogic::XNOR); 3, NetLogic::XNOR);
connect(gate->pin(0), osig->pin(0)); connect(gate->pin(0), osig->pin(0));
connect(gate->pin(1), lsig->pin(0)); connect(gate->pin(1), lsig->pin(0));
@ -148,7 +154,7 @@ NetNet* NetEBComp::synthesize(Design*des)
operation. This is similar to single bit equality, but uses operation. This is similar to single bit equality, but uses
an XOR instead of an XNOR gate. */ an XOR instead of an XNOR gate. */
if ((width == 1) && ((op_ == 'n') || (op_ == 'N'))) { if ((width == 1) && ((op_ == 'n') || (op_ == 'N'))) {
NetLogic*gate = new NetLogic(des->local_symbol(path), NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
3, NetLogic::XOR); 3, NetLogic::XOR);
connect(gate->pin(0), osig->pin(0)); connect(gate->pin(0), osig->pin(0));
connect(gate->pin(1), lsig->pin(0)); connect(gate->pin(1), lsig->pin(0));
@ -258,10 +264,13 @@ NetNet* NetEConst::synthesize(Design*des)
*/ */
NetNet* NetEUBits::synthesize(Design*des) NetNet* NetEUBits::synthesize(Design*des)
{ {
string path = des->local_symbol("SYNTH");
NetNet*isig = expr_->synthesize(des); NetNet*isig = expr_->synthesize(des);
NetNet*osig = new NetNet(isig->scope(), path, NetNet::IMPLICIT, NetScope*scope = isig->scope();
assert(scope);
string path = des->local_symbol(scope->name());
NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT,
isig->pin_count()); isig->pin_count());
osig->local_flag(true); osig->local_flag(true);
@ -271,7 +280,7 @@ NetNet* NetEUBits::synthesize(Design*des)
switch (op()) { switch (op()) {
case '~': case '~':
gate = new NetLogic(oname, 2, NetLogic::NOT); gate = new NetLogic(scope, oname, 2, NetLogic::NOT);
break; break;
default: default:
assert(0); assert(0);
@ -320,6 +329,9 @@ NetNet* NetESignal::synthesize(Design*des)
/* /*
* $Log: expr_synth.cc,v $ * $Log: expr_synth.cc,v $
* Revision 1.15 2000/10/07 19:45:43 steve
* Put logic devices into scopes.
*
* Revision 1.14 2000/05/02 00:58:12 steve * Revision 1.14 2000/05/02 00:58:12 steve
* Move signal tables to the NetScope class. * Move signal tables to the NetScope class.
* *

20
ivl_target.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: ivl_target.h,v 1.16 2000/10/06 23:46:50 steve Exp $" #ident "$Id: ivl_target.h,v 1.17 2000/10/07 19:45:43 steve Exp $"
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
@ -72,6 +72,12 @@ _BEGIN_DECL
* processes. Structural expressions are instead treated as logic * processes. Structural expressions are instead treated as logic
* gates. * gates.
* *
* ivl_net_logic_t
* This object represents various built in logic devices. In fact,
* this includes just about every directional device that has a
* single output, including logic gates and nmos, pmos and cmon
* devices. There is also the occasional Icarus Verilog creation.
*
* ivl_process_t * ivl_process_t
* A Verilog process is represented by one of these. A process may * A Verilog process is represented by one of these. A process may
* be an "initial" or an "always" process. These come from initial * be an "initial" or an "always" process. These come from initial
@ -100,7 +106,6 @@ _BEGIN_DECL
*/ */
typedef struct ivl_design_s *ivl_design_t; typedef struct ivl_design_s *ivl_design_t;
typedef struct ivl_expr_s *ivl_expr_t; typedef struct ivl_expr_s *ivl_expr_t;
typedef struct ivl_net_bufz_s *ivl_net_bufz_t;
typedef struct ivl_net_const_s*ivl_net_const_t; typedef struct ivl_net_const_s*ivl_net_const_t;
typedef struct ivl_net_event_s*ivl_net_event_t; typedef struct ivl_net_event_s*ivl_net_event_t;
typedef struct ivl_net_logic_s*ivl_net_logic_t; typedef struct ivl_net_logic_s*ivl_net_logic_t;
@ -135,6 +140,7 @@ typedef enum ivl_logic_e {
IVL_LO_BUF, IVL_LO_BUF,
IVL_LO_BUFIF0, IVL_LO_BUFIF0,
IVL_LO_BUFIF1, IVL_LO_BUFIF1,
IVL_LO_BUFZ,
IVL_LO_NAND, IVL_LO_NAND,
IVL_LO_NOR, IVL_LO_NOR,
IVL_LO_NOT, IVL_LO_NOT,
@ -369,13 +375,6 @@ typedef int (*start_design_f)(ivl_design_t des);
typedef void (*end_design_f)(ivl_design_t des); typedef void (*end_design_f)(ivl_design_t des);
/* target_net_bufz
The "target_net_bufz" function is called for all the BUFZ devices
in the netlist. */
typedef int (*net_bufz_f)(const char*name, ivl_net_bufz_t net);
/* target_net_const /* target_net_const
The "target_net_const" function is called for structural constant The "target_net_const" function is called for structural constant
@ -443,6 +442,9 @@ _END_DECL
/* /*
* $Log: ivl_target.h,v $ * $Log: ivl_target.h,v $
* Revision 1.17 2000/10/07 19:45:43 steve
* Put logic devices into scopes.
*
* Revision 1.16 2000/10/06 23:46:50 steve * Revision 1.16 2000/10/06 23:46:50 steve
* ivl_target updates, including more complete * ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced * handling of ivl_nexus_t objects. Much reduced

18
netlist.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: netlist.cc,v 1.141 2000/10/06 23:46:50 steve Exp $" #ident "$Id: netlist.cc,v 1.142 2000/10/07 19:45:43 steve Exp $"
#endif #endif
# include <cassert> # include <cassert>
@ -258,6 +258,11 @@ NetNode::NetNode(const string&n, unsigned npins)
{ {
} }
NetNode::NetNode(NetScope*s, const string&n, unsigned npins)
: NetObj(s, n, npins), node_next_(0), node_prev_(0), design_(0)
{
}
NetNode::~NetNode() NetNode::~NetNode()
{ {
if (design_) if (design_)
@ -1468,8 +1473,8 @@ const NetProc* NetBlock::proc_next(const NetProc*cur) const
return cur->next_; return cur->next_;
} }
NetBUFZ::NetBUFZ(const string&n) NetBUFZ::NetBUFZ(NetScope*s, const string&n)
: NetNode(n, 2) : NetNode(s, n, 2)
{ {
pin(0).set_dir(Link::OUTPUT); pin(0).set_dir(Link::OUTPUT);
pin(1).set_dir(Link::INPUT); pin(1).set_dir(Link::INPUT);
@ -2239,8 +2244,8 @@ NetEUBits::~NetEUBits()
{ {
} }
NetLogic::NetLogic(const string&n, unsigned pins, TYPE t) NetLogic::NetLogic(NetScope*s, const string&n, unsigned pins, TYPE t)
: NetNode(n, pins), type_(t) : NetNode(s, n, pins), type_(t)
{ {
pin(0).set_dir(Link::OUTPUT); pin(0).set_dir(Link::OUTPUT);
pin(0).set_name("O", 0); pin(0).set_name("O", 0);
@ -2436,6 +2441,9 @@ bool NetUDP::sequ_glob_(string input, char output)
/* /*
* $Log: netlist.cc,v $ * $Log: netlist.cc,v $
* Revision 1.142 2000/10/07 19:45:43 steve
* Put logic devices into scopes.
*
* Revision 1.141 2000/10/06 23:46:50 steve * Revision 1.141 2000/10/06 23:46:50 steve
* ivl_target updates, including more complete * ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced * handling of ivl_nexus_t objects. Much reduced

10
netlist.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: netlist.h,v 1.172 2000/10/06 23:46:50 steve Exp $" #ident "$Id: netlist.h,v 1.173 2000/10/07 19:45:43 steve Exp $"
#endif #endif
/* /*
@ -270,6 +270,7 @@ class Nexus {
class NetNode : public NetObj { class NetNode : public NetObj {
public: public:
explicit NetNode(NetScope*s, const string&n, unsigned npins);
explicit NetNode(const string&n, unsigned npins); explicit NetNode(const string&n, unsigned npins);
virtual ~NetNode(); virtual ~NetNode();
@ -907,7 +908,7 @@ class NetTmp : public NetNet {
class NetBUFZ : public NetNode { class NetBUFZ : public NetNode {
public: public:
explicit NetBUFZ(const string&n); explicit NetBUFZ(NetScope*s, const string&n);
~NetBUFZ(); ~NetBUFZ();
virtual void dump_node(ostream&, unsigned ind) const; virtual void dump_node(ostream&, unsigned ind) const;
@ -976,7 +977,7 @@ class NetLogic : public NetNode {
enum TYPE { AND, BUF, BUFIF0, BUFIF1, NAND, NOR, NOT, NOTIF0, enum TYPE { AND, BUF, BUFIF0, BUFIF1, NAND, NOR, NOT, NOTIF0,
NOTIF1, OR, XNOR, XOR }; NOTIF1, OR, XNOR, XOR };
explicit NetLogic(const string&n, unsigned pins, TYPE t); explicit NetLogic(NetScope*s, const string&n, unsigned pins, TYPE t);
TYPE type() const { return type_; } TYPE type() const { return type_; }
@ -2805,6 +2806,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
/* /*
* $Log: netlist.h,v $ * $Log: netlist.h,v $
* Revision 1.173 2000/10/07 19:45:43 steve
* Put logic devices into scopes.
*
* Revision 1.172 2000/10/06 23:46:50 steve * Revision 1.172 2000/10/06 23:46:50 steve
* ivl_target updates, including more complete * ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced * handling of ivl_nexus_t objects. Much reduced

111
t-dll.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: t-dll.cc,v 1.11 2000/10/06 23:46:51 steve Exp $" #ident "$Id: t-dll.cc,v 1.12 2000/10/07 19:45:43 steve Exp $"
#endif #endif
# include "compiler.h" # include "compiler.h"
@ -27,6 +27,46 @@
static struct dll_target dll_target_obj; static struct dll_target dll_target_obj;
/*
* This function locates an ivl_scope_t object that matches the
* NetScope object. The search works by looking for the parent scope,
* then scanning the parent scope for the NetScope object.
*/
static ivl_scope_t find_scope(ivl_scope_t root, const NetScope*cur)
{
ivl_scope_t parent, tmp;
if (const NetScope*par = cur->parent()) {
parent = find_scope(root, par);
} else {
assert(root->self == cur);
return root;
}
for (tmp = parent->child_ ; tmp ; tmp = tmp->sibling_)
if (tmp->self == cur)
return tmp;
return 0;
}
void scope_add_logic(ivl_scope_t scope, ivl_net_logic_t net)
{
if (scope->nlog_ == 0) {
scope->nlog_ = 1;
scope->log_ = (ivl_net_logic_t*)malloc(sizeof(ivl_net_logic_t));
scope->log_[0] = net;
} else {
scope->nlog_ += 1;
scope->log_ = (ivl_net_logic_t*)
realloc(scope->log_, scope->nlog_*sizeof(ivl_net_logic_t));
scope->log_[scope->nlog_-1] = net;
}
}
bool dll_target::start_design(const Design*des) bool dll_target::start_design(const Design*des)
{ {
dll_path_ = des->get_flag("DLL"); dll_path_ = des->get_flag("DLL");
@ -46,7 +86,6 @@ bool dll_target::start_design(const Design*des)
start_design_ = (start_design_f)dlsym(dll_, LU "target_start_design" TU); start_design_ = (start_design_f)dlsym(dll_, LU "target_start_design" TU);
end_design_ = (end_design_f) dlsym(dll_, LU "target_end_design" TU); end_design_ = (end_design_f) dlsym(dll_, LU "target_end_design" TU);
net_bufz_ = (net_bufz_f) dlsym(dll_, LU "target_net_bufz" TU);
net_const_ = (net_const_f) dlsym(dll_, LU "target_net_const" TU); net_const_ = (net_const_f) dlsym(dll_, LU "target_net_const" TU);
net_event_ = (net_event_f) dlsym(dll_, LU "target_net_event" TU); net_event_ = (net_event_f) dlsym(dll_, LU "target_net_event" TU);
net_logic_ = (net_logic_f) dlsym(dll_, LU "target_net_logic" TU); net_logic_ = (net_logic_f) dlsym(dll_, LU "target_net_logic" TU);
@ -67,17 +106,36 @@ void dll_target::end_design(const Design*)
bool dll_target::bufz(const NetBUFZ*net) bool dll_target::bufz(const NetBUFZ*net)
{ {
if (net_bufz_) { struct ivl_net_logic_s *obj = new struct ivl_net_logic_s;
int rc = (net_bufz_)(net->name(), 0);
return rc == 0; assert(net->pin_count() == 2);
obj->type_ = IVL_LO_BUFZ;
obj->npins_ = 2;
obj->pins_ = new ivl_nexus_t[2];
assert(net->pin(0).nexus()->t_cookie());
obj->pins_[0] = (ivl_nexus_t) net->pin(0).nexus()->t_cookie();
assert(net->pin(1).nexus()->t_cookie());
obj->pins_[1] = (ivl_nexus_t) net->pin(1).nexus()->t_cookie();
assert(net->scope());
ivl_scope_t scope = find_scope(des_.root_, net->scope());
assert(scope);
scope_add_logic(scope, obj);
if (net_logic_) {
(net_logic_)(net->name(), obj);
} else { } else {
cerr << dll_path_ << ": internal error: target DLL lacks " cerr << dll_path_ << ": internal error: target DLL lacks "
<< "target_net_bufz function." << endl; << "target_net_logic function." << endl;
return false;
} }
return false; return true;
} }
void dll_target::event(const NetEvent*net) void dll_target::event(const NetEvent*net)
@ -124,6 +182,12 @@ void dll_target::logic(const NetLogic*net)
obj->pins_[idx] = (ivl_nexus_t) nex->t_cookie(); obj->pins_[idx] = (ivl_nexus_t) nex->t_cookie();
} }
assert(net->scope());
ivl_scope_t scope = find_scope(des_.root_, net->scope());
assert(scope);
scope_add_logic(scope, obj);
if (net_logic_) { if (net_logic_) {
(net_logic_)(net->name(), obj); (net_logic_)(net->name(), obj);
@ -131,8 +195,6 @@ void dll_target::logic(const NetLogic*net)
cerr << dll_path_ << ": internal error: target DLL lacks " cerr << dll_path_ << ": internal error: target DLL lacks "
<< "target_net_logic function." << endl; << "target_net_logic function." << endl;
} }
return;
} }
bool dll_target::net_const(const NetConst*net) bool dll_target::net_const(const NetConst*net)
@ -213,30 +275,6 @@ void dll_target::net_probe(const NetEvProbe*net)
return; return;
} }
/*
* This function locates an ivl_scope_t object that matches the
* NetScope object. The search works by looking for the parent scope,
* then scanning the parent scope for the NetScope object.
*/
static ivl_scope_t find_scope(ivl_scope_t root, const NetScope*cur)
{
ivl_scope_t parent, tmp;
if (const NetScope*par = cur->parent()) {
parent = find_scope(root, par);
} else {
assert(root->self == cur);
return root;
}
for (tmp = parent->child_ ; tmp ; tmp = tmp->sibling_)
if (tmp->self == cur)
return tmp;
return 0;
}
void dll_target::scope(const NetScope*net) void dll_target::scope(const NetScope*net)
{ {
ivl_scope_t scope; ivl_scope_t scope;
@ -246,7 +284,7 @@ void dll_target::scope(const NetScope*net)
scope = des_.root_; scope = des_.root_;
} else { } else {
scope = (ivl_scope_t)calloc(1, sizeof(struct ivl_scope_s)); scope = new struct ivl_scope_s;
scope->self = net; scope->self = net;
ivl_scope_t parent = find_scope(des_.root_, net->parent()); ivl_scope_t parent = find_scope(des_.root_, net->parent());
@ -425,6 +463,9 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
/* /*
* $Log: t-dll.cc,v $ * $Log: t-dll.cc,v $
* Revision 1.12 2000/10/07 19:45:43 steve
* Put logic devices into scopes.
*
* Revision 1.11 2000/10/06 23:46:51 steve * Revision 1.11 2000/10/06 23:46:51 steve
* ivl_target updates, including more complete * ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced * handling of ivl_nexus_t objects. Much reduced

9
t-dll.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: t-dll.h,v 1.9 2000/10/06 23:46:51 steve Exp $" #ident "$Id: t-dll.h,v 1.10 2000/10/07 19:45:43 steve Exp $"
#endif #endif
# include "target.h" # include "target.h"
@ -60,7 +60,6 @@ struct dll_target : public target_t, public expr_scan_t {
start_design_f start_design_; start_design_f start_design_;
end_design_f end_design_; end_design_f end_design_;
net_bufz_f net_bufz_;
net_const_f net_const_; net_const_f net_const_;
net_event_f net_event_; net_event_f net_event_;
net_logic_f net_logic_; net_logic_f net_logic_;
@ -188,6 +187,9 @@ struct ivl_scope_s {
unsigned nsigs_; unsigned nsigs_;
ivl_signal_t*sigs_; ivl_signal_t*sigs_;
unsigned nlog_;
ivl_net_logic_t*log_;
}; };
/* /*
@ -270,6 +272,9 @@ struct ivl_statement_s {
/* /*
* $Log: t-dll.h,v $ * $Log: t-dll.h,v $
* Revision 1.10 2000/10/07 19:45:43 steve
* Put logic devices into scopes.
*
* Revision 1.9 2000/10/06 23:46:51 steve * Revision 1.9 2000/10/06 23:46:51 steve
* ivl_target updates, including more complete * ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced * handling of ivl_nexus_t objects. Much reduced

15
tgt-stub/stub.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: stub.c,v 1.14 2000/10/06 23:46:51 steve Exp $" #ident "$Id: stub.c,v 1.15 2000/10/07 19:45:43 steve Exp $"
#endif #endif
/* /*
@ -54,12 +54,6 @@ void target_end_design(ivl_design_t des)
fclose(out); fclose(out);
} }
int target_net_bufz(const char*name, ivl_net_bufz_t net)
{
fprintf(out, "STUB: %s: BUFZ\n", name);
return 0;
}
int target_net_const(const char*name, ivl_net_const_t net) int target_net_const(const char*name, ivl_net_const_t net)
{ {
unsigned idx; unsigned idx;
@ -100,6 +94,10 @@ int target_net_logic(const char*name, ivl_net_logic_t net)
fprintf(out, "buf %s (%s", name, fprintf(out, "buf %s (%s", name,
ivl_nexus_name(ivl_logic_pin(net, 0))); ivl_nexus_name(ivl_logic_pin(net, 0)));
break; break;
case IVL_LO_BUFZ:
fprintf(out, "bufz %s (%s", name,
ivl_nexus_name(ivl_logic_pin(net, 0)));
break;
case IVL_LO_OR: case IVL_LO_OR:
fprintf(out, "or %s (%s", name, fprintf(out, "or %s (%s", name,
ivl_nexus_name(ivl_logic_pin(net, 0))); ivl_nexus_name(ivl_logic_pin(net, 0)));
@ -301,6 +299,9 @@ int target_process(ivl_process_t net)
/* /*
* $Log: stub.c,v $ * $Log: stub.c,v $
* Revision 1.15 2000/10/07 19:45:43 steve
* Put logic devices into scopes.
*
* Revision 1.14 2000/10/06 23:46:51 steve * Revision 1.14 2000/10/06 23:46:51 steve
* ivl_target updates, including more complete * ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced * handling of ivl_nexus_t objects. Much reduced

23
tgt-verilog/verilog.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: verilog.c,v 1.8 2000/10/06 23:46:51 steve Exp $" #ident "$Id: verilog.c,v 1.9 2000/10/07 19:45:43 steve Exp $"
#endif #endif
/* /*
@ -55,12 +55,6 @@ void target_end_design(ivl_design_t des)
fclose(out); fclose(out);
} }
int target_net_bufz(const char*name, ivl_net_bufz_t net)
{
fprintf(out, "STUB: %s: BUFZ\n", name);
return 0;
}
int target_net_const(const char*name, ivl_net_const_t net) int target_net_const(const char*name, ivl_net_const_t net)
{ {
fprintf(out, "STUB: %s: constant\n", name); fprintf(out, "STUB: %s: constant\n", name);
@ -144,8 +138,18 @@ static void show_expression(ivl_expr_t net)
switch (ivl_expr_type(net)) { switch (ivl_expr_type(net)) {
case IVL_EX_BINARY: { case IVL_EX_BINARY: {
char code = ivl_expr_opcode(net);
show_expression(ivl_expr_oper1(net)); show_expression(ivl_expr_oper1(net));
fprintf(out, "%c", ivl_expr_opcode(net)); switch (code) {
case 'e':
fprintf(out, "==");
break;
case 'n':
fprintf(out, "!=");
break;
default:
fprintf(out, "%c", code);
}
show_expression(ivl_expr_oper2(net)); show_expression(ivl_expr_oper2(net));
break; break;
} }
@ -280,6 +284,9 @@ int target_process(ivl_process_t net)
/* /*
* $Log: verilog.c,v $ * $Log: verilog.c,v $
* Revision 1.9 2000/10/07 19:45:43 steve
* Put logic devices into scopes.
*
* Revision 1.8 2000/10/06 23:46:51 steve * Revision 1.8 2000/10/06 23:46:51 steve
* ivl_target updates, including more complete * ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced * handling of ivl_nexus_t objects. Much reduced

23
xnfio.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) && !defined(macintosh) #if !defined(WINNT) && !defined(macintosh)
#ident "$Id: xnfio.cc,v 1.15 2000/06/25 19:59:42 steve Exp $" #ident "$Id: xnfio.cc,v 1.16 2000/10/07 19:45:43 steve Exp $"
#endif #endif
# include "functor.h" # include "functor.h"
@ -55,6 +55,9 @@ static bool is_a_pad(const NetNet*net)
static NetLogic* make_obuf(Design*des, NetNet*net) static NetLogic* make_obuf(Design*des, NetNet*net)
{ {
NetScope* scope = net->scope();
assert(scope);
assert(net->pin_count() == 1); assert(net->pin_count() == 1);
/* FIXME: If there is nothing internally driving this PAD, I /* FIXME: If there is nothing internally driving this PAD, I
@ -123,7 +126,8 @@ static NetLogic* make_obuf(Design*des, NetNet*net)
// Can't seem to find a way to rearrange the existing netlist, // Can't seem to find a way to rearrange the existing netlist,
// so I am stuck creating a new buffer, the OBUF. // so I am stuck creating a new buffer, the OBUF.
NetLogic*buf = new NetLogic(des->local_symbol("$"), 2, NetLogic::BUF); NetLogic*buf = new NetLogic(scope, des->local_symbol(scope->name()),
2, NetLogic::BUF);
des->add_node(buf); des->add_node(buf);
map<string,string>attr; map<string,string>attr;
@ -140,8 +144,7 @@ static NetLogic* make_obuf(Design*des, NetNet*net)
// of the netlist, to create a ring without a signal. Detect // of the netlist, to create a ring without a signal. Detect
// this case and create a new signal. // this case and create a new signal.
if (count_signals(buf->pin(1)) == 0) { if (count_signals(buf->pin(1)) == 0) {
NetNet*tmp = new NetNet(net->scope(), NetNet*tmp = new NetNet(scope, des->local_symbol(scope->name()),
des->local_symbol("$"),
NetNet::WIRE); NetNet::WIRE);
tmp->local_flag(true); tmp->local_flag(true);
connect(buf->pin(1), tmp->pin(0)); connect(buf->pin(1), tmp->pin(0));
@ -235,7 +238,8 @@ static void make_ibuf(Design*des, NetNet*net)
} }
// I give up, create an IBUF. // I give up, create an IBUF.
NetLogic*buf = new NetLogic(des->local_symbol("$"), 2, NetLogic::BUF); NetLogic*buf = new NetLogic(scope, des->local_symbol(scope->name()),
2, NetLogic::BUF);
des->add_node(buf); des->add_node(buf);
map<string,string>attr; map<string,string>attr;
@ -309,6 +313,8 @@ bool xnfio_f::compare_sideb_const(Design*des, NetCompare*dev)
if (dev->width() > 4) if (dev->width() > 4)
return false; return false;
NetScope*scope = des->find_root_scope();
verinum side (verinum::V0, dev->width()); verinum side (verinum::V0, dev->width());
/* Is the B side all constant? */ /* Is the B side all constant? */
@ -325,7 +331,7 @@ bool xnfio_f::compare_sideb_const(Design*des, NetCompare*dev)
/* Handle the special case of comparing A to 0. Use an N-input /* Handle the special case of comparing A to 0. Use an N-input
NOR gate to return 0 if any of the bits is not 0. */ NOR gate to return 0 if any of the bits is not 0. */
if ((side.as_ulong() == 0) && (count_inputs(dev->pin_AEB()) > 0)) { if ((side.as_ulong() == 0) && (count_inputs(dev->pin_AEB()) > 0)) {
NetLogic*sub = new NetLogic(dev->name(), dev->width()+1, NetLogic*sub = new NetLogic(scope, dev->name(), dev->width()+1,
NetLogic::NOR); NetLogic::NOR);
connect(sub->pin(0), dev->pin_AEB()); connect(sub->pin(0), dev->pin_AEB());
for (unsigned idx = 0 ; idx < dev->width() ; idx += 1) for (unsigned idx = 0 ; idx < dev->width() ; idx += 1)
@ -338,7 +344,7 @@ bool xnfio_f::compare_sideb_const(Design*des, NetCompare*dev)
/* Handle the special case of comparing A to 0. Use an N-input /* Handle the special case of comparing A to 0. Use an N-input
NOR gate to return 0 if any of the bits is not 0. */ NOR gate to return 0 if any of the bits is not 0. */
if ((side.as_ulong() == 0) && (count_inputs(dev->pin_ANEB()) > 0)) { if ((side.as_ulong() == 0) && (count_inputs(dev->pin_ANEB()) > 0)) {
NetLogic*sub = new NetLogic(dev->name(), dev->width()+1, NetLogic*sub = new NetLogic(scope, dev->name(), dev->width()+1,
NetLogic::OR); NetLogic::OR);
connect(sub->pin(0), dev->pin_ANEB()); connect(sub->pin(0), dev->pin_ANEB());
for (unsigned idx = 0 ; idx < dev->width() ; idx += 1) for (unsigned idx = 0 ; idx < dev->width() ; idx += 1)
@ -359,6 +365,9 @@ void xnfio(Design*des)
/* /*
* $Log: xnfio.cc,v $ * $Log: xnfio.cc,v $
* Revision 1.16 2000/10/07 19:45:43 steve
* Put logic devices into scopes.
*
* Revision 1.15 2000/06/25 19:59:42 steve * Revision 1.15 2000/06/25 19:59:42 steve
* Redesign Links to include the Nexus class that * Redesign Links to include the Nexus class that
* carries properties of the connected set of links. * carries properties of the connected set of links.