From 76e2c509d7668ece11387465b48727b578efffb5 Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Sat, 7 Oct 2000 19:45:42 +0000
Subject: [PATCH]  Put logic devices into scopes.

---
 cprop.cc              |  24 ++++++---
 design_dump.cc        |   9 +++-
 elab_net.cc           |  81 +++++++++++++++---------------
 elaborate.cc          |  44 ++++++++++++-----
 expr_synth.cc         |  42 ++++++++++------
 ivl_target.h          |  20 ++++----
 netlist.cc            |  18 +++++--
 netlist.h             |  10 ++--
 t-dll.cc              | 111 +++++++++++++++++++++++++++++-------------
 t-dll.h               |   9 +++-
 tgt-stub/stub.c       |  15 +++---
 tgt-verilog/verilog.c |  23 ++++++---
 xnfio.cc              |  23 ++++++---
 13 files changed, 275 insertions(+), 154 deletions(-)

diff --git a/cprop.cc b/cprop.cc
index 93e5bd9f2..70ca5bbff 100644
--- a/cprop.cc
+++ b/cprop.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: cprop.cc,v 1.16 2000/10/06 21:26:34 steve Exp $"
+#ident "$Id: cprop.cc,v 1.17 2000/10/07 19:45:42 steve Exp $"
 #endif
 
 # include  "netlist.h"
@@ -108,14 +108,15 @@ void cprop_functor::lpm_add_sub(Design*des, NetAddSub*obj)
       if (obj->width() == 1) {
 	    NetLogic*tmp;
 	    if (obj->pin_Cout().is_linked()) {
-		  tmp = new NetLogic(des->local_symbol(obj->name()), 3,
-						       NetLogic::AND);
+		  tmp = new NetLogic(obj->scope(),
+				     des->local_symbol(obj->name()), 3,
+				     NetLogic::AND);
 		  connect(tmp->pin(0), obj->pin_Cout());
 		  connect(tmp->pin(1), obj->pin_DataA(0));
 		  connect(tmp->pin(2), obj->pin_DataB(0));
 		  des->add_node(tmp);
 	    }
-	    tmp = new NetLogic(obj->name(), 3, NetLogic::XOR);
+	    tmp = new NetLogic(obj->scope(), obj->name(), 3, NetLogic::XOR);
 	    connect(tmp->pin(0), obj->pin_Result(0));
 	    connect(tmp->pin(1), obj->pin_DataA(0));
 	    connect(tmp->pin(2), obj->pin_DataB(0));
@@ -246,7 +247,8 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		}
 
 		if (top == 2) {
-		      NetLogic*tmp = new NetLogic(obj->name(), top,
+		      NetLogic*tmp = new NetLogic(obj->scope(),
+						  obj->name(), top,
 						  NetLogic::BUF);
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
@@ -259,7 +261,8 @@ void cprop_functor::lpm_logic(Design*des, NetLogic*obj)
 		}
 
 		if (top < obj->pin_count()) {
-		      NetLogic*tmp = new NetLogic(obj->name(), top,
+		      NetLogic*tmp = new NetLogic(obj->scope(),
+						  obj->name(), top,
 						  NetLogic::XOR);
 		      des->add_node(tmp);
 		      tmp->pin(0).drive0(obj->pin(0).drive0());
@@ -307,7 +310,8 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
 
       if (flag) {
 	    for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-		  NetLogic*tmp = new NetLogic(des->local_symbol(obj->name()),
+		  NetLogic*tmp = new NetLogic(obj->scope(),
+					      des->local_symbol(obj->name()),
 					      3, NetLogic::BUFIF1);
 
 		  connect(obj->pin_Result(idx), tmp->pin(0));
@@ -338,7 +342,8 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
 
       if (flag) {
 	    for (unsigned idx = 0 ;  idx < obj->width() ;  idx += 1) {
-		  NetLogic*tmp = new NetLogic(des->local_symbol(obj->name()),
+		  NetLogic*tmp = new NetLogic(obj->scope(),
+					      des->local_symbol(obj->name()),
 					      3, NetLogic::BUFIF0);
 
 		  connect(obj->pin_Result(idx), tmp->pin(0));
@@ -428,6 +433,9 @@ void cprop(Design*des)
 
 /*
  * $Log: cprop.cc,v $
+ * Revision 1.17  2000/10/07 19:45:42  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.16  2000/10/06 21:26:34  steve
  *  Eliminate zero inputs to xor.
  *
diff --git a/design_dump.cc b/design_dump.cc
index a6cf069d1..89375a8d7 100644
--- a/design_dump.cc
+++ b/design_dump.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: design_dump.cc,v 1.99 2000/10/06 23:46:50 steve Exp $"
+#ident "$Id: design_dump.cc,v 1.100 2000/10/07 19:45:42 steve Exp $"
 #endif
 
 /*
@@ -228,7 +228,8 @@ void NetAssign_::dump_node(ostream&o, unsigned ind) const
 
 void NetBUFZ::dump_node(ostream&o, unsigned ind) const
 {
-      o << setw(ind) << "" << "NetBUFZ: " << name() << endl;
+      o << setw(ind) << "" << "NetBUFZ: " << name()
+	<< " scope=" << (scope()? scope()->name() : "") << endl;
       dump_node_pins(o, ind+4);
 }
 
@@ -291,6 +292,7 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
       }
       o << " #(" << rise_time()
 	<< "," << fall_time() << "," << decay_time() << ") " << name()
+	<< " scope=" << (scope()? scope()->name() : "")
 	<< endl;
 
       dump_node_pins(o, ind+4);
@@ -971,6 +973,9 @@ void Design::dump(ostream&o) const
 
 /*
  * $Log: design_dump.cc,v $
+ * Revision 1.100  2000/10/07 19:45:42  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.99  2000/10/06 23:46:50  steve
  *  ivl_target updates, including more complete
  *  handling of ivl_nexus_t objects. Much reduced
diff --git a/elab_net.cc b/elab_net.cc
index 2ba6a6c3f..e156d5953 100644
--- a/elab_net.cc
+++ b/elab_net.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elab_net.cc,v 1.48 2000/09/26 05:05:58 steve Exp $"
+#ident "$Id: elab_net.cc,v 1.49 2000/10/07 19:45:42 steve Exp $"
 #endif
 
 # include  "PExpr.h"
@@ -264,8 +264,8 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, const string&path,
       switch (op_) {
 	  case '^': // XOR
 	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1) {
-		  NetLogic*gate = new NetLogic(des->local_symbol(path), 3,
-				      NetLogic::XOR);
+		  NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
+					       3, NetLogic::XOR);
 		  connect(gate->pin(1), lsig->pin(idx));
 		  connect(gate->pin(2), rsig->pin(idx));
 		  connect(gate->pin(0), osig->pin(idx));
@@ -278,8 +278,8 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, const string&path,
 
 	  case 'X': // XNOR
 	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1) {
-		  NetLogic*gate = new NetLogic(des->local_symbol(path), 3,
-				      NetLogic::XNOR);
+		  NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
+					       3, NetLogic::XNOR);
 		  connect(gate->pin(1), lsig->pin(idx));
 		  connect(gate->pin(2), rsig->pin(idx));
 		  connect(gate->pin(0), osig->pin(idx));
@@ -292,8 +292,8 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, const string&path,
 
 	  case '&': // AND
 	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1) {
-		  NetLogic*gate = new NetLogic(des->local_symbol(path), 3,
-				      NetLogic::AND);
+		  NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
+					       3, NetLogic::AND);
 		  connect(gate->pin(1), lsig->pin(idx));
 		  connect(gate->pin(2), rsig->pin(idx));
 		  connect(gate->pin(0), osig->pin(idx));
@@ -306,7 +306,7 @@ NetNet* PEBinary::elaborate_net_bit_(Design*des, const string&path,
 
 	  case '|': // Bitwise OR
 	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1) {
-		  NetLogic*gate = new NetLogic(des->local_symbol(path),
+		  NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
 					       3, NetLogic::OR);
 		  connect(gate->pin(1), lsig->pin(idx));
 		  connect(gate->pin(2), rsig->pin(idx));
@@ -412,7 +412,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
 	  case 'E': // Case equals (===)
 	      // The comparison generates gates to bitwise compare
 	      // each pair, and AND all the comparison results.
-	    gate = new NetLogic(des->local_symbol(path),
+	    gate = new NetLogic(scope, des->local_symbol(path),
 				1+lsig->pin_count(),
 				NetLogic::AND);
 	    connect(gate->pin(0), osig->pin(0));
@@ -446,7 +446,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
 	      /* Handle the special case of single bit compare with a
 		 single XNOR gate. This is easy and direct. */
 	    if (dwidth == 1) {
-		  gate = new NetLogic(des->local_symbol(path),
+		  gate = new NetLogic(scope, des->local_symbol(path),
 				      3, NetLogic::XNOR);
 		  connect(gate->pin(0), osig->pin(0));
 		  connect(gate->pin(1), lsig->pin(0));
@@ -455,11 +455,11 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
 	    }
 
 	      /* Oh well, do the general case. */
-	    gate = new NetLogic(des->local_symbol(path),
+	    gate = new NetLogic(scope, des->local_symbol(path),
 				1+dwidth,NetLogic::AND);
 	    connect(gate->pin(0), osig->pin(0));
 	    for (unsigned idx = 0 ;  idx < dwidth ;  idx += 1) {
-		  NetLogic*cmp = new NetLogic(des->local_symbol(path),
+		  NetLogic*cmp = new NetLogic(scope, des->local_symbol(path),
 					      3, NetLogic::XNOR);
 		  if (idx < lsig->pin_count())
 			connect(cmp->pin(1), lsig->pin(idx));
@@ -487,7 +487,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
 	      /* Handle the special case of single bit compare with a
 		 single XOR gate. This is easy and direct. */
 	    if (dwidth == 1) {
-		  gate = new NetLogic(des->local_symbol(path),
+		  gate = new NetLogic(scope, des->local_symbol(path),
 				      3, NetLogic::XOR);
 		  connect(gate->pin(0), osig->pin(0));
 		  connect(gate->pin(1), lsig->pin(0));
@@ -495,12 +495,12 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, const string&path,
 		  break;
 	    }
 
-	    gate = new NetLogic(des->local_symbol(path),
+	    gate = new NetLogic(scope, des->local_symbol(path),
 				1+dwidth, NetLogic::OR);
 	    connect(gate->pin(0), osig->pin(0));
 	    for (unsigned idx = 0 ;  idx < dwidth ;  idx += 1) {
-		  NetLogic*cmp = new NetLogic(des->local_symbol(path), 3,
-					      NetLogic::XOR);
+		  NetLogic*cmp = new NetLogic(scope, des->local_symbol(path),
+					      3, NetLogic::XOR);
 		  if (idx < lsig->pin_count())
 			connect(cmp->pin(1), lsig->pin(idx));
 		  else
@@ -665,10 +665,12 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, const string&path,
       NetLogic*gate_t;
       switch (op_) {
 	  case 'a':
-	    gate = new NetLogic(des->local_symbol(path), 3, NetLogic::AND);
+	    gate = new NetLogic(scope, des->local_symbol(path),
+				3, NetLogic::AND);
 	    break;
 	  case 'o':
-	    gate = new NetLogic(des->local_symbol(path), 3, NetLogic::OR);
+	    gate = new NetLogic(scope, des->local_symbol(path),
+				3, NetLogic::OR);
 	    break;
 	  default:
 	    assert(0);
@@ -679,7 +681,7 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, const string&path,
 
 	// The first OR gate returns 1 if the left value is true...
       if (lsig->pin_count() > 1) {
-	    gate_t = new NetLogic(des->local_symbol(path),
+	    gate_t = new NetLogic(scope, des->local_symbol(path),
 				  1+lsig->pin_count(), NetLogic::OR);
 	    for (unsigned idx = 0 ;  idx < lsig->pin_count() ;  idx += 1)
 		  connect(gate_t->pin(idx+1), lsig->pin(idx));
@@ -699,7 +701,7 @@ NetNet* PEBinary::elaborate_net_log_(Design*des, const string&path,
 
 	// The second OR gate returns 1 if the right value is true...
       if (rsig->pin_count() > 1) {
-	    gate_t = new NetLogic(des->local_symbol(path),
+	    gate_t = new NetLogic(scope, des->local_symbol(path),
 				  1+rsig->pin_count(), NetLogic::OR);
 	    for (unsigned idx = 0 ;  idx < rsig->pin_count() ;  idx += 1)
 		  connect(gate_t->pin(idx+1), rsig->pin(idx));
@@ -1536,7 +1538,7 @@ NetNet* PETernary::elaborate_net(Design*des, const string&path,
 	   by connecting an OR gate to calculate the truth value of
 	   the result. In the end, the result needs to be a single bit. */
       if (expr_sig->pin_count() > 1) {
-	    NetLogic*log = new NetLogic(des->local_symbol(path),
+	    NetLogic*log = new NetLogic(scope, des->local_symbol(path),
 					expr_sig->pin_count()+1,
 					NetLogic::OR);
 	    for (unsigned idx = 0;  idx < expr_sig->pin_count(); idx += 1)
@@ -1642,8 +1644,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
 			     sub_sig->pin_count());
 	    sig->local_flag(true);
 	    for (unsigned idx = 0 ;  idx < sub_sig->pin_count() ;  idx += 1) {
-		  gate = new NetLogic(des->local_symbol(path), 2,
-				      NetLogic::NOT);
+		  gate = new NetLogic(scope, des->local_symbol(path),
+				      2, NetLogic::NOT);
 		  connect(gate->pin(1), sub_sig->pin(idx));
 		  connect(gate->pin(0), sig->pin(idx));
 		  des->add_node(gate);
@@ -1657,9 +1659,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
 	  case '!': // Reduction NOT
 	    sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
 	    sig->local_flag(true);
-	    gate = new NetLogic(des->local_symbol(path),
-				1+sub_sig->pin_count(),
-				NetLogic::NOR);
+	    gate = new NetLogic(scope, des->local_symbol(path),
+				1+sub_sig->pin_count(), NetLogic::NOR);
 	    connect(gate->pin(0), sig->pin(0));
 	    for (unsigned idx = 0 ;  idx < sub_sig->pin_count() ;  idx += 1)
 		  connect(gate->pin(idx+1), sub_sig->pin(idx));
@@ -1673,9 +1674,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
 	  case '&': // Reduction AND
 	    sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
 	    sig->local_flag(true);
-	    gate = new NetLogic(des->local_symbol(path),
-				1+sub_sig->pin_count(),
-				NetLogic::AND);
+	    gate = new NetLogic(scope, des->local_symbol(path),
+				1+sub_sig->pin_count(), NetLogic::AND);
 	    connect(gate->pin(0), sig->pin(0));
 	    for (unsigned idx = 0 ;  idx < sub_sig->pin_count() ;  idx += 1)
 		  connect(gate->pin(idx+1), sub_sig->pin(idx));
@@ -1689,9 +1689,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
 	  case '|': // Reduction OR
 	    sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
 	    sig->local_flag(true);
-	    gate = new NetLogic(des->local_symbol(path),
-				1+sub_sig->pin_count(),
-				NetLogic::OR);
+	    gate = new NetLogic(scope, des->local_symbol(path),
+				1+sub_sig->pin_count(), NetLogic::OR);
 	    connect(gate->pin(0), sig->pin(0));
 	    for (unsigned idx = 0 ;  idx < sub_sig->pin_count() ;  idx += 1)
 		  connect(gate->pin(idx+1), sub_sig->pin(idx));
@@ -1705,9 +1704,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
 	  case '^': // Reduction XOR
 	    sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
 	    sig->local_flag(true);
-	    gate = new NetLogic(des->local_symbol(path),
-				1+sub_sig->pin_count(),
-				NetLogic::XOR);
+	    gate = new NetLogic(scope, des->local_symbol(path),
+				1+sub_sig->pin_count(), NetLogic::XOR);
 	    connect(gate->pin(0), sig->pin(0));
 	    for (unsigned idx = 0 ;  idx < sub_sig->pin_count() ;  idx += 1)
 		  connect(gate->pin(idx+1), sub_sig->pin(idx));
@@ -1721,9 +1719,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
 	  case 'A': // Reduction NAND (~&)
 	    sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
 	    sig->local_flag(true);
-	    gate = new NetLogic(des->local_symbol(path),
-				1+sub_sig->pin_count(),
-				NetLogic::NAND);
+	    gate = new NetLogic(scope, des->local_symbol(path),
+				1+sub_sig->pin_count(), NetLogic::NAND);
 	    connect(gate->pin(0), sig->pin(0));
 	    for (unsigned idx = 0 ;  idx < sub_sig->pin_count() ;  idx += 1)
 		  connect(gate->pin(idx+1), sub_sig->pin(idx));
@@ -1738,9 +1735,8 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
 	  case 'X': // Reduction XNOR (~^)
 	    sig = new NetNet(scope, des->local_symbol(path), NetNet::WIRE);
 	    sig->local_flag(true);
-	    gate = new NetLogic(des->local_symbol(path),
-				1+sub_sig->pin_count(),
-				NetLogic::XNOR);
+	    gate = new NetLogic(scope, des->local_symbol(path),
+				1+sub_sig->pin_count(), NetLogic::XNOR);
 	    connect(gate->pin(0), sig->pin(0));
 	    for (unsigned idx = 0 ;  idx < sub_sig->pin_count() ;  idx += 1)
 		  connect(gate->pin(idx+1), sub_sig->pin(idx));
@@ -1764,6 +1760,9 @@ NetNet* PEUnary::elaborate_net(Design*des, const string&path,
 
 /*
  * $Log: elab_net.cc,v $
+ * Revision 1.49  2000/10/07 19:45:42  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.48  2000/09/26 05:05:58  steve
  *  Detect indefinite widths where definite widths are required.
  *
diff --git a/elaborate.cc b/elaborate.cc
index 5b98e5ac1..7ccb43346 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: elaborate.cc,v 1.192 2000/09/29 22:58:57 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.193 2000/10/07 19:45:42 steve Exp $"
 #endif
 
 /*
@@ -73,6 +73,9 @@ void PGate::elaborate(Design*des, const string&path) const
  */
 void PGAssign::elaborate(Design*des, const string&path) const
 {
+      NetScope*scope = des->find_scope(path);
+      assert(scope);
+
       unsigned long rise_time, fall_time, decay_time;
       eval_delays(des, path, rise_time, fall_time, decay_time);
 
@@ -132,7 +135,8 @@ void PGAssign::elaborate(Design*des, const string&path) const
 	    } else {
 		  unsigned idx;
 		  for (idx = 0 ; idx < cnt ;  idx += 1) {
-			NetBUFZ*dev = new NetBUFZ(des->local_symbol(path));
+			NetBUFZ*dev = new NetBUFZ(scope,
+						  des->local_symbol(path));
 			connect(lval->pin(idx), dev->pin(0));
 			connect(rid->pin(idx), dev->pin(1));
 			dev->pin(0).drive0(drive0);
@@ -198,6 +202,9 @@ void PGBuiltin::elaborate(Design*des, const string&path) const
       unsigned count = 1;
       unsigned low = 0, high = 0;
       string name = get_name();
+
+      NetScope*scope = des->find_scope(path);
+
       if (name == "")
 	    name = des->local_symbol(path);
       else
@@ -270,34 +277,44 @@ void PGBuiltin::elaborate(Design*des, const string&path) const
 
 	    switch (type()) {
 		case AND:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::AND);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::AND);
 		  break;
 		case BUF:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUF);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::BUF);
 		  break;
 		case BUFIF0:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUFIF0);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::BUFIF0);
 		  break;
 		case BUFIF1:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::BUFIF1);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::BUFIF1);
 		  break;
 		case NAND:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NAND);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::NAND);
 		  break;
 		case NOR:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NOR);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::NOR);
 		  break;
 		case NOT:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::NOT);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::NOT);
 		  break;
 		case OR:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::OR);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::OR);
 		  break;
 		case XNOR:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::XNOR);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::XNOR);
 		  break;
 		case XOR:
-		  cur[idx] = new NetLogic(inm, pin_count(), NetLogic::XOR);
+		  cur[idx] = new NetLogic(scope, inm, pin_count(),
+					  NetLogic::XOR);
 		  break;
 		default:
 		  cerr << get_line() << ": internal error: unhandled "
@@ -2265,6 +2282,9 @@ Design* elaborate(const map<string,Module*>&modules,
 
 /*
  * $Log: elaborate.cc,v $
+ * Revision 1.193  2000/10/07 19:45:42  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.192  2000/09/29 22:58:57  steve
  *  Do not put noop statements into blocks.
  *
diff --git a/expr_synth.cc b/expr_synth.cc
index 07bbd18d0..a1e434d39 100644
--- a/expr_synth.cc
+++ b/expr_synth.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: expr_synth.cc,v 1.14 2000/05/02 00:58:12 steve Exp $"
+#ident "$Id: expr_synth.cc,v 1.15 2000/10/07 19:45:43 steve Exp $"
 #endif
 
 # include  "netlist.h"
@@ -76,12 +76,15 @@ NetNet* NetEBAdd::synthesize(Design*des)
  */
 NetNet* NetEBBits::synthesize(Design*des)
 {
-      string path = des->local_symbol("SYNTH");
       NetNet*lsig = left_->synthesize(des);
       NetNet*rsig = right_->synthesize(des);
 
+      NetScope*scope = lsig->scope();
+      assert(scope);
+      string path = des->local_symbol(scope->name());
+
       assert(lsig->pin_count() == rsig->pin_count());
-      NetNet*osig = new NetNet(lsig->scope(), path, NetNet::IMPLICIT,
+      NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT,
 			       lsig->pin_count());
       osig->local_flag(true);
 
@@ -91,19 +94,19 @@ NetNet* NetEBBits::synthesize(Design*des)
 
 	    switch (op()) {
 		case '&':
-		  gate = new NetLogic(oname, 3, NetLogic::AND);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::AND);
 		  break;
 		case '|':
-		  gate = new NetLogic(oname, 3, NetLogic::OR);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::OR);
 		  break;
 		case '^':
-		  gate = new NetLogic(oname, 3, NetLogic::XOR);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::XOR);
 		  break;
 		case 'O':
-		  gate = new NetLogic(oname, 3, NetLogic::NOR);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::NOR);
 		  break;
 		case 'X':
-		  gate = new NetLogic(oname, 3, NetLogic::XNOR);
+		  gate = new NetLogic(scope, oname, 3, NetLogic::XNOR);
 		  break;
 		default:
 		  assert(0);
@@ -121,21 +124,24 @@ NetNet* NetEBBits::synthesize(Design*des)
 
 NetNet* NetEBComp::synthesize(Design*des)
 {
-      string path = des->local_symbol("SYNTH");
       NetNet*lsig = left_->synthesize(des);
       NetNet*rsig = right_->synthesize(des);
 
+      NetScope*scope = lsig->scope();
+      assert(scope);
+      string path = des->local_symbol(scope->name());
+
       unsigned width = lsig->pin_count();
       if (rsig->pin_count() > lsig->pin_count())
 	    width = rsig->pin_count();
 
-      NetNet*osig = new NetNet(lsig->scope(), path, NetNet::IMPLICIT, 1);
+      NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT, 1);
       osig->local_flag(true);
 
 	/* Handle the special case of a single bit equality
 	   operation. Make an XNOR gate instead of a comparator. */
       if ((width == 1) && ((op_ == 'e') || (op_ == 'E'))) {
-	    NetLogic*gate = new NetLogic(des->local_symbol(path),
+	    NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
 					 3, NetLogic::XNOR);
 	    connect(gate->pin(0), osig->pin(0));
 	    connect(gate->pin(1), lsig->pin(0));
@@ -148,7 +154,7 @@ NetNet* NetEBComp::synthesize(Design*des)
 	   operation. This is similar to single bit equality, but uses
 	   an XOR instead of an XNOR gate. */
       if ((width == 1) && ((op_ == 'n') || (op_ == 'N'))) {
-	    NetLogic*gate = new NetLogic(des->local_symbol(path),
+	    NetLogic*gate = new NetLogic(scope, des->local_symbol(path),
 					 3, NetLogic::XOR);
 	    connect(gate->pin(0), osig->pin(0));
 	    connect(gate->pin(1), lsig->pin(0));
@@ -258,10 +264,13 @@ NetNet* NetEConst::synthesize(Design*des)
  */
 NetNet* NetEUBits::synthesize(Design*des)
 {
-      string path = des->local_symbol("SYNTH");
       NetNet*isig = expr_->synthesize(des);
 
-      NetNet*osig = new NetNet(isig->scope(), path, NetNet::IMPLICIT,
+      NetScope*scope = isig->scope();
+      assert(scope);
+      string path = des->local_symbol(scope->name());
+
+      NetNet*osig = new NetNet(scope, path, NetNet::IMPLICIT,
 			       isig->pin_count());
       osig->local_flag(true);
 
@@ -271,7 +280,7 @@ NetNet* NetEUBits::synthesize(Design*des)
 
 	    switch (op()) {
 		case '~':
-		  gate = new NetLogic(oname, 2, NetLogic::NOT);
+		  gate = new NetLogic(scope, oname, 2, NetLogic::NOT);
 		  break;
 		default:
 		  assert(0);
@@ -320,6 +329,9 @@ NetNet* NetESignal::synthesize(Design*des)
 
 /*
  * $Log: expr_synth.cc,v $
+ * Revision 1.15  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.14  2000/05/02 00:58:12  steve
  *  Move signal tables to the NetScope class.
  *
diff --git a/ivl_target.h b/ivl_target.h
index 3d29b541e..a4150f076 100644
--- a/ivl_target.h
+++ b/ivl_target.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: ivl_target.h,v 1.16 2000/10/06 23:46:50 steve Exp $"
+#ident "$Id: ivl_target.h,v 1.17 2000/10/07 19:45:43 steve Exp $"
 #endif
 
 #ifdef __cplusplus
@@ -72,6 +72,12 @@ _BEGIN_DECL
  *    processes. Structural expressions are instead treated as logic
  *    gates.
  *
+ * ivl_net_logic_t
+ *    This object represents various built in logic devices. In fact,
+ *    this includes just about every directional device that has a
+ *    single output, including logic gates and nmos, pmos and cmon
+ *    devices. There is also the occasional Icarus Verilog creation.
+ *
  * ivl_process_t
  *    A Verilog process is represented by one of these. A process may
  *    be an "initial" or an "always" process. These come from initial
@@ -100,7 +106,6 @@ _BEGIN_DECL
  */
 typedef struct ivl_design_s   *ivl_design_t;
 typedef struct ivl_expr_s     *ivl_expr_t;
-typedef struct ivl_net_bufz_s *ivl_net_bufz_t;
 typedef struct ivl_net_const_s*ivl_net_const_t;
 typedef struct ivl_net_event_s*ivl_net_event_t;
 typedef struct ivl_net_logic_s*ivl_net_logic_t;
@@ -135,6 +140,7 @@ typedef enum ivl_logic_e {
       IVL_LO_BUF,
       IVL_LO_BUFIF0,
       IVL_LO_BUFIF1,
+      IVL_LO_BUFZ,
       IVL_LO_NAND,
       IVL_LO_NOR,
       IVL_LO_NOT,
@@ -369,13 +375,6 @@ typedef int  (*start_design_f)(ivl_design_t des);
 typedef void (*end_design_f)(ivl_design_t des);
 
 
-/* target_net_bufz
-
-   The "target_net_bufz" function is called for all the BUFZ devices
-   in the netlist. */
-typedef int (*net_bufz_f)(const char*name, ivl_net_bufz_t net);
-
-
 /* target_net_const
 
    The "target_net_const" function is called for structural constant
@@ -443,6 +442,9 @@ _END_DECL
 
 /*
  * $Log: ivl_target.h,v $
+ * Revision 1.17  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.16  2000/10/06 23:46:50  steve
  *  ivl_target updates, including more complete
  *  handling of ivl_nexus_t objects. Much reduced
diff --git a/netlist.cc b/netlist.cc
index 7f8d8548c..6b7de0f40 100644
--- a/netlist.cc
+++ b/netlist.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: netlist.cc,v 1.141 2000/10/06 23:46:50 steve Exp $"
+#ident "$Id: netlist.cc,v 1.142 2000/10/07 19:45:43 steve Exp $"
 #endif
 
 # include  <cassert>
@@ -258,6 +258,11 @@ NetNode::NetNode(const string&n, unsigned npins)
 {
 }
 
+NetNode::NetNode(NetScope*s, const string&n, unsigned npins)
+: NetObj(s, n, npins), node_next_(0), node_prev_(0), design_(0)
+{
+}
+
 NetNode::~NetNode()
 {
       if (design_)
@@ -1468,8 +1473,8 @@ const NetProc* NetBlock::proc_next(const NetProc*cur) const
       return cur->next_;
 }
 
-NetBUFZ::NetBUFZ(const string&n)
-: NetNode(n, 2)
+NetBUFZ::NetBUFZ(NetScope*s, const string&n)
+: NetNode(s, n, 2)
 {
       pin(0).set_dir(Link::OUTPUT);
       pin(1).set_dir(Link::INPUT);
@@ -2239,8 +2244,8 @@ NetEUBits::~NetEUBits()
 {
 }
 
-NetLogic::NetLogic(const string&n, unsigned pins, TYPE t)
-: NetNode(n, pins), type_(t)
+NetLogic::NetLogic(NetScope*s, const string&n, unsigned pins, TYPE t)
+: NetNode(s, n, pins), type_(t)
 {
       pin(0).set_dir(Link::OUTPUT);
       pin(0).set_name("O", 0);
@@ -2436,6 +2441,9 @@ bool NetUDP::sequ_glob_(string input, char output)
 
 /*
  * $Log: netlist.cc,v $
+ * Revision 1.142  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.141  2000/10/06 23:46:50  steve
  *  ivl_target updates, including more complete
  *  handling of ivl_nexus_t objects. Much reduced
diff --git a/netlist.h b/netlist.h
index 5ecca336a..b339afcd6 100644
--- a/netlist.h
+++ b/netlist.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: netlist.h,v 1.172 2000/10/06 23:46:50 steve Exp $"
+#ident "$Id: netlist.h,v 1.173 2000/10/07 19:45:43 steve Exp $"
 #endif
 
 /*
@@ -270,6 +270,7 @@ class Nexus {
 class NetNode  : public NetObj {
 
     public:
+      explicit NetNode(NetScope*s, const string&n, unsigned npins);
       explicit NetNode(const string&n, unsigned npins);
 
       virtual ~NetNode();
@@ -907,7 +908,7 @@ class NetTmp  : public NetNet {
 class NetBUFZ  : public NetNode {
 
     public:
-      explicit NetBUFZ(const string&n);
+      explicit NetBUFZ(NetScope*s, const string&n);
       ~NetBUFZ();
 
       virtual void dump_node(ostream&, unsigned ind) const;
@@ -976,7 +977,7 @@ class NetLogic  : public NetNode {
       enum TYPE { AND, BUF, BUFIF0, BUFIF1, NAND, NOR, NOT, NOTIF0,
 		  NOTIF1, OR, XNOR, XOR };
 
-      explicit NetLogic(const string&n, unsigned pins, TYPE t);
+      explicit NetLogic(NetScope*s, const string&n, unsigned pins, TYPE t);
 
       TYPE type() const { return type_; }
 
@@ -2805,6 +2806,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
 
 /*
  * $Log: netlist.h,v $
+ * Revision 1.173  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.172  2000/10/06 23:46:50  steve
  *  ivl_target updates, including more complete
  *  handling of ivl_nexus_t objects. Much reduced
diff --git a/t-dll.cc b/t-dll.cc
index d40bdba73..e99e92bf1 100644
--- a/t-dll.cc
+++ b/t-dll.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: t-dll.cc,v 1.11 2000/10/06 23:46:51 steve Exp $"
+#ident "$Id: t-dll.cc,v 1.12 2000/10/07 19:45:43 steve Exp $"
 #endif
 
 # include  "compiler.h"
@@ -27,6 +27,46 @@
 
 static struct dll_target dll_target_obj;
 
+/*
+ * This function locates an ivl_scope_t object that matches the
+ * NetScope object. The search works by looking for the parent scope,
+ * then scanning the parent scope for the NetScope object.
+ */
+static ivl_scope_t find_scope(ivl_scope_t root, const NetScope*cur)
+{
+      ivl_scope_t parent, tmp;
+
+      if (const NetScope*par = cur->parent()) {
+	    parent = find_scope(root, par);
+
+      } else {
+	    assert(root->self == cur);
+	    return root;
+      }
+
+      for (tmp = parent->child_ ;  tmp ;  tmp = tmp->sibling_)
+	    if (tmp->self == cur)
+		  return tmp;
+
+      return 0;
+}
+
+void scope_add_logic(ivl_scope_t scope, ivl_net_logic_t net)
+{
+      if (scope->nlog_ == 0) {
+	    scope->nlog_ = 1;
+	    scope->log_ = (ivl_net_logic_t*)malloc(sizeof(ivl_net_logic_t));
+	    scope->log_[0] = net;
+
+      } else {
+	    scope->nlog_ += 1;
+	    scope->log_ = (ivl_net_logic_t*)
+		  realloc(scope->log_, scope->nlog_*sizeof(ivl_net_logic_t));
+	    scope->log_[scope->nlog_-1] = net;
+      }
+
+}
+
 bool dll_target::start_design(const Design*des)
 {
       dll_path_ = des->get_flag("DLL");
@@ -46,7 +86,6 @@ bool dll_target::start_design(const Design*des)
       start_design_ = (start_design_f)dlsym(dll_, LU "target_start_design" TU);
       end_design_   = (end_design_f)  dlsym(dll_, LU "target_end_design" TU);
 
-      net_bufz_   = (net_bufz_f)  dlsym(dll_, LU "target_net_bufz" TU);
       net_const_  = (net_const_f) dlsym(dll_, LU "target_net_const" TU);
       net_event_  = (net_event_f) dlsym(dll_, LU "target_net_event" TU);
       net_logic_  = (net_logic_f) dlsym(dll_, LU "target_net_logic" TU);
@@ -67,17 +106,36 @@ void dll_target::end_design(const Design*)
 
 bool dll_target::bufz(const NetBUFZ*net)
 {
-      if (net_bufz_) {
-	    int rc = (net_bufz_)(net->name(), 0);
-	    return rc == 0;
+      struct ivl_net_logic_s *obj = new struct ivl_net_logic_s;
+
+      assert(net->pin_count() == 2);
+
+      obj->type_ = IVL_LO_BUFZ;
+
+      obj->npins_ = 2;
+      obj->pins_ = new ivl_nexus_t[2];
+
+      assert(net->pin(0).nexus()->t_cookie());
+      obj->pins_[0] = (ivl_nexus_t) net->pin(0).nexus()->t_cookie();
+
+      assert(net->pin(1).nexus()->t_cookie());
+      obj->pins_[1] = (ivl_nexus_t) net->pin(1).nexus()->t_cookie();
+
+      assert(net->scope());
+      ivl_scope_t scope = find_scope(des_.root_, net->scope());
+      assert(scope);
+
+      scope_add_logic(scope, obj);
+
+      if (net_logic_) {
+	    (net_logic_)(net->name(), obj);
 
       } else {
 	    cerr << dll_path_ << ": internal error: target DLL lacks "
-		 << "target_net_bufz function." << endl;
-	    return false;
+		 << "target_net_logic function." << endl;
       }
 
-      return false;
+      return true;
 }
 
 void dll_target::event(const NetEvent*net)
@@ -124,6 +182,12 @@ void dll_target::logic(const NetLogic*net)
 	    obj->pins_[idx] = (ivl_nexus_t) nex->t_cookie();
       }
 
+      assert(net->scope());
+      ivl_scope_t scope = find_scope(des_.root_, net->scope());
+      assert(scope);
+
+      scope_add_logic(scope, obj);
+
       if (net_logic_) {
 	    (net_logic_)(net->name(), obj);
 
@@ -131,8 +195,6 @@ void dll_target::logic(const NetLogic*net)
 	    cerr << dll_path_ << ": internal error: target DLL lacks "
 		 << "target_net_logic function." << endl;
       }
-
-      return;
 }
 
 bool dll_target::net_const(const NetConst*net)
@@ -213,30 +275,6 @@ void dll_target::net_probe(const NetEvProbe*net)
       return;
 }
 
-/*
- * This function locates an ivl_scope_t object that matches the
- * NetScope object. The search works by looking for the parent scope,
- * then scanning the parent scope for the NetScope object.
- */
-static ivl_scope_t find_scope(ivl_scope_t root, const NetScope*cur)
-{
-      ivl_scope_t parent, tmp;
-
-      if (const NetScope*par = cur->parent()) {
-	    parent = find_scope(root, par);
-
-      } else {
-	    assert(root->self == cur);
-	    return root;
-      }
-
-      for (tmp = parent->child_ ;  tmp ;  tmp = tmp->sibling_)
-	    if (tmp->self == cur)
-		  return tmp;
-
-      return 0;
-}
-      
 void dll_target::scope(const NetScope*net)
 {
       ivl_scope_t scope;
@@ -246,7 +284,7 @@ void dll_target::scope(const NetScope*net)
 	    scope = des_.root_;
 
       } else {
-	    scope = (ivl_scope_t)calloc(1, sizeof(struct ivl_scope_s));
+	    scope = new struct ivl_scope_s;
 	    scope->self = net;
 
 	    ivl_scope_t parent = find_scope(des_.root_, net->parent());
@@ -425,6 +463,9 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
 
 /*
  * $Log: t-dll.cc,v $
+ * Revision 1.12  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.11  2000/10/06 23:46:51  steve
  *  ivl_target updates, including more complete
  *  handling of ivl_nexus_t objects. Much reduced
diff --git a/t-dll.h b/t-dll.h
index 5e9650c3f..41f7a9310 100644
--- a/t-dll.h
+++ b/t-dll.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: t-dll.h,v 1.9 2000/10/06 23:46:51 steve Exp $"
+#ident "$Id: t-dll.h,v 1.10 2000/10/07 19:45:43 steve Exp $"
 #endif
 
 # include  "target.h"
@@ -60,7 +60,6 @@ struct dll_target  : public target_t, public expr_scan_t {
       start_design_f start_design_;
       end_design_f   end_design_;
 
-      net_bufz_f   net_bufz_;
       net_const_f  net_const_;
       net_event_f  net_event_;
       net_logic_f  net_logic_;
@@ -188,6 +187,9 @@ struct ivl_scope_s {
 
       unsigned nsigs_;
       ivl_signal_t*sigs_;
+
+      unsigned nlog_;
+      ivl_net_logic_t*log_;
 };
 
 /*
@@ -270,6 +272,9 @@ struct ivl_statement_s {
 
 /*
  * $Log: t-dll.h,v $
+ * Revision 1.10  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.9  2000/10/06 23:46:51  steve
  *  ivl_target updates, including more complete
  *  handling of ivl_nexus_t objects. Much reduced
diff --git a/tgt-stub/stub.c b/tgt-stub/stub.c
index 563939968..5697ff281 100644
--- a/tgt-stub/stub.c
+++ b/tgt-stub/stub.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: stub.c,v 1.14 2000/10/06 23:46:51 steve Exp $"
+#ident "$Id: stub.c,v 1.15 2000/10/07 19:45:43 steve Exp $"
 #endif
 
 /*
@@ -54,12 +54,6 @@ void target_end_design(ivl_design_t des)
       fclose(out);
 }
 
-int target_net_bufz(const char*name, ivl_net_bufz_t net)
-{
-      fprintf(out, "STUB: %s: BUFZ\n", name);
-      return 0;
-}
-
 int target_net_const(const char*name, ivl_net_const_t net)
 {
       unsigned idx;
@@ -100,6 +94,10 @@ int target_net_logic(const char*name, ivl_net_logic_t net)
 	    fprintf(out, "buf %s (%s", name,
 		    ivl_nexus_name(ivl_logic_pin(net, 0)));
 	    break;
+	  case IVL_LO_BUFZ:
+	    fprintf(out, "bufz %s (%s", name,
+		    ivl_nexus_name(ivl_logic_pin(net, 0)));
+	    break;
 	  case IVL_LO_OR:
 	    fprintf(out, "or %s (%s", name,
 		    ivl_nexus_name(ivl_logic_pin(net, 0)));
@@ -301,6 +299,9 @@ int target_process(ivl_process_t net)
 
 /*
  * $Log: stub.c,v $
+ * Revision 1.15  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.14  2000/10/06 23:46:51  steve
  *  ivl_target updates, including more complete
  *  handling of ivl_nexus_t objects. Much reduced
diff --git a/tgt-verilog/verilog.c b/tgt-verilog/verilog.c
index 1addd6f82..e785887bc 100644
--- a/tgt-verilog/verilog.c
+++ b/tgt-verilog/verilog.c
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: verilog.c,v 1.8 2000/10/06 23:46:51 steve Exp $"
+#ident "$Id: verilog.c,v 1.9 2000/10/07 19:45:43 steve Exp $"
 #endif
 
 /*
@@ -55,12 +55,6 @@ void target_end_design(ivl_design_t des)
       fclose(out);
 }
 
-int target_net_bufz(const char*name, ivl_net_bufz_t net)
-{
-      fprintf(out, "STUB: %s: BUFZ\n", name);
-      return 0;
-}
-
 int target_net_const(const char*name, ivl_net_const_t net)
 {
       fprintf(out, "STUB: %s: constant\n", name);
@@ -144,8 +138,18 @@ static void show_expression(ivl_expr_t net)
       switch (ivl_expr_type(net)) {
 
 	  case IVL_EX_BINARY: {
+		char code = ivl_expr_opcode(net);
 		show_expression(ivl_expr_oper1(net));
-		fprintf(out, "%c", ivl_expr_opcode(net));
+		switch (code) {
+		    case 'e':
+		      fprintf(out, "==");
+		      break;
+		    case 'n':
+		      fprintf(out, "!=");
+		      break;
+		    default:
+		      fprintf(out, "%c", code);
+		}
 		show_expression(ivl_expr_oper2(net));
 		break;
 	  }
@@ -280,6 +284,9 @@ int target_process(ivl_process_t net)
 
 /*
  * $Log: verilog.c,v $
+ * Revision 1.9  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.8  2000/10/06 23:46:51  steve
  *  ivl_target updates, including more complete
  *  handling of ivl_nexus_t objects. Much reduced
diff --git a/xnfio.cc b/xnfio.cc
index 035656773..9b384275e 100644
--- a/xnfio.cc
+++ b/xnfio.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: xnfio.cc,v 1.15 2000/06/25 19:59:42 steve Exp $"
+#ident "$Id: xnfio.cc,v 1.16 2000/10/07 19:45:43 steve Exp $"
 #endif
 
 # include  "functor.h"
@@ -55,6 +55,9 @@ static bool is_a_pad(const NetNet*net)
 
 static NetLogic* make_obuf(Design*des, NetNet*net)
 {
+      NetScope* scope = net->scope();
+      assert(scope);
+
       assert(net->pin_count() == 1);
 
 	/* FIXME: If there is nothing internally driving this PAD, I
@@ -123,7 +126,8 @@ static NetLogic* make_obuf(Design*des, NetNet*net)
 
 	// Can't seem to find a way to rearrange the existing netlist,
 	// so I am stuck creating a new buffer, the OBUF.
-      NetLogic*buf = new NetLogic(des->local_symbol("$"), 2, NetLogic::BUF);
+      NetLogic*buf = new NetLogic(scope, des->local_symbol(scope->name()),
+				  2, NetLogic::BUF);
       des->add_node(buf);
 
       map<string,string>attr;
@@ -140,8 +144,7 @@ static NetLogic* make_obuf(Design*des, NetNet*net)
 	// of the netlist, to create a ring without a signal. Detect
 	// this case and create a new signal.
       if (count_signals(buf->pin(1)) == 0) {
-	    NetNet*tmp = new NetNet(net->scope(),
-				    des->local_symbol("$"),
+	    NetNet*tmp = new NetNet(scope, des->local_symbol(scope->name()),
 				    NetNet::WIRE);
 	    tmp->local_flag(true);
 	    connect(buf->pin(1), tmp->pin(0));
@@ -235,7 +238,8 @@ static void make_ibuf(Design*des, NetNet*net)
       }
 
 	// I give up, create an IBUF.
-      NetLogic*buf = new NetLogic(des->local_symbol("$"), 2, NetLogic::BUF);
+      NetLogic*buf = new NetLogic(scope, des->local_symbol(scope->name()),
+				  2, NetLogic::BUF);
       des->add_node(buf);
 
       map<string,string>attr;
@@ -309,6 +313,8 @@ bool xnfio_f::compare_sideb_const(Design*des, NetCompare*dev)
       if (dev->width() > 4)
 	    return false;
 
+      NetScope*scope = des->find_root_scope();
+
       verinum side (verinum::V0, dev->width());
 
 	/* Is the B side all constant? */
@@ -325,7 +331,7 @@ bool xnfio_f::compare_sideb_const(Design*des, NetCompare*dev)
 	/* Handle the special case of comparing A to 0. Use an N-input
 	   NOR gate to return 0 if any of the bits is not 0. */
       if ((side.as_ulong() == 0) && (count_inputs(dev->pin_AEB()) > 0)) {
-	    NetLogic*sub = new NetLogic(dev->name(), dev->width()+1,
+	    NetLogic*sub = new NetLogic(scope, dev->name(), dev->width()+1,
 					NetLogic::NOR);
 	    connect(sub->pin(0), dev->pin_AEB());
 	    for (unsigned idx = 0 ;  idx < dev->width() ;  idx += 1)
@@ -338,7 +344,7 @@ bool xnfio_f::compare_sideb_const(Design*des, NetCompare*dev)
 	/* Handle the special case of comparing A to 0. Use an N-input
 	   NOR gate to return 0 if any of the bits is not 0. */
       if ((side.as_ulong() == 0) && (count_inputs(dev->pin_ANEB()) > 0)) {
-	    NetLogic*sub = new NetLogic(dev->name(), dev->width()+1,
+	    NetLogic*sub = new NetLogic(scope, dev->name(), dev->width()+1,
 					NetLogic::OR);
 	    connect(sub->pin(0), dev->pin_ANEB());
 	    for (unsigned idx = 0 ;  idx < dev->width() ;  idx += 1)
@@ -359,6 +365,9 @@ void xnfio(Design*des)
 
 /*
  * $Log: xnfio.cc,v $
+ * Revision 1.16  2000/10/07 19:45:43  steve
+ *  Put logic devices into scopes.
+ *
  * Revision 1.15  2000/06/25 19:59:42  steve
  *  Redesign Links to include the Nexus class that
  *  carries properties of the connected set of links.