From 6adc3c9f1314338607bd57a6a4852a0256110217 Mon Sep 17 00:00:00 2001 From: Nick Gasson Date: Sun, 17 Aug 2008 19:42:07 +0100 Subject: [PATCH] Add short section on VHDL to man page --- driver/iverilog.man | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/driver/iverilog.man b/driver/iverilog.man index 05d936a1d..3c74e9feb 100644 --- a/driver/iverilog.man +++ b/driver/iverilog.man @@ -223,6 +223,12 @@ mostly by EDIF format output. The Icarus Verilog fpga code generator can generate complete designs or EDIF macros that can in turn be imported into larger designs by other tools. The \fBfpga\fP target implies the synthesis \fB-S\fP flag. +.TP 8 +.B vhdl +This target produces a VHDL translation of the Verilog netlist. The +output is a single file containing VHDL entities corresponding to +the modules in the Verilog source code. Note that only a subset of +the Verilog language is supported. See the wiki for more information. .SH "WARNING TYPES" These are the types of warnings that can be selected by the \fB-W\fP