diff --git a/elaborate.cc b/elaborate.cc
index 834ef7fb6..7439c5617 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: elaborate.cc,v 1.41 1999/06/13 04:46:54 steve Exp $"
+#ident "$Id: elaborate.cc,v 1.42 1999/06/13 16:30:06 steve Exp $"
 #endif
 
 /*
@@ -1056,7 +1056,10 @@ NetProc* PAssign::elaborate(Design*des, const string&path) const
       }
       assert(rval);
 
-      NetAssign*cur = new NetAssign(des, reg, rval);
+      NetAssign*cur = new NetAssign("@assign", des, reg, rval);
+      for (unsigned idx = 0 ;  idx < cur->pin_count() ;  idx += 1)
+	    connect(cur->pin(idx), reg->pin(idx));
+
       cur->set_line(*this);
       des->add_node(cur);
 
@@ -1369,8 +1372,11 @@ NetProc* PForStatement::elaborate(Design*des, const string&path) const
 	    return 0;
       }
       assert(sig);
-      NetAssign*init = new NetAssign(des, sig,
+      NetAssign*init = new NetAssign("@for-assign", des, sig,
 				     expr1_->elaborate_expr(des, path));
+      for (unsigned idx = 0 ;  idx < init->pin_count() ;  idx += 1)
+	    connect(init->pin(idx), sig->pin(idx));
+
       top->append(init);
 
       NetBlock*body = new NetBlock(NetBlock::SEQU);
@@ -1379,8 +1385,11 @@ NetProc* PForStatement::elaborate(Design*des, const string&path) const
 
       sig = des->find_signal(path+"."+id2->name());
       assert(sig);
-      NetAssign*step = new NetAssign(des, sig,
+      NetAssign*step = new NetAssign("@for-assign", des, sig,
 				     expr2_->elaborate_expr(des, path));
+      for (unsigned idx = 0 ;  idx < step->pin_count() ;  idx += 1)
+	    connect(step->pin(idx), sig->pin(idx));
+
       body->append(step);
 
       NetWhile*loop = new NetWhile(cond_->elaborate_expr(des, path), body);
@@ -1498,6 +1507,9 @@ Design* elaborate(const map<string,Module*>&modules,
 
 /*
  * $Log: elaborate.cc,v $
+ * Revision 1.42  1999/06/13 16:30:06  steve
+ *  Unify the NetAssign constructors a bit.
+ *
  * Revision 1.41  1999/06/13 04:46:54  steve
  *  Add part select lvalues to AssignNB.
  *
diff --git a/netlist.cc b/netlist.cc
index be57ea4c7..7d8b6f3d0 100644
--- a/netlist.cc
+++ b/netlist.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: netlist.cc,v 1.35 1999/06/10 05:33:28 steve Exp $"
+#ident "$Id: netlist.cc,v 1.36 1999/06/13 16:30:06 steve Exp $"
 #endif
 
 # include  <cassert>
@@ -273,14 +273,21 @@ NetProc::~NetProc()
 {
 }
 
-NetAssign::NetAssign(Design*des, NetNet*lv, NetExpr*rv)
-: NetNode("@assign", lv->pin_count()), rval_(rv)
+NetAssign_::NetAssign_(const string&n, unsigned w)
+: NetNode(n, w)
 {
-      for (unsigned idx = 0 ;  idx < pin_count() ;  idx += 1) {
+      for (unsigned idx = 0 ;  idx < pin_count() ;  idx += 1)
 	    pin(idx).set_dir(NetObj::Link::OUTPUT);
-	    connect(pin(idx), lv->pin(idx));
-      }
 
+}
+
+NetAssign_::~NetAssign_()
+{
+}
+
+NetAssign::NetAssign(const string&n, Design*des, NetNet*lv, NetExpr*rv)
+: NetAssign_(n, lv->pin_count()), rval_(rv)
+{
       bool flag = rval_->set_width(lv->pin_count());
       if (flag == false) {
 	    cerr << rv->get_line() << ": Expression bit width" <<
@@ -294,12 +301,8 @@ NetAssign::~NetAssign()
 }
 
 NetAssignNB::NetAssignNB(const string&n, Design*des, unsigned w, NetExpr*rv)
-: NetNode(n, w), rval_(rv), bmux_(0)
+: NetAssign_(n, w), rval_(rv), bmux_(0)
 {
-      for (unsigned idx = 0 ;  idx < pin_count() ;  idx += 1) {
-	    pin(idx).set_dir(NetObj::Link::OUTPUT);
-      }
-
       bool flag = rval_->set_width(w);
       if (flag == false) {
 	    cerr << rv->get_line() << ": Expression bit width" <<
@@ -310,12 +313,8 @@ NetAssignNB::NetAssignNB(const string&n, Design*des, unsigned w, NetExpr*rv)
 
 NetAssignNB::NetAssignNB(const string&n, Design*des, unsigned w,
 			 NetExpr*mu, NetExpr*rv)
-: NetNode(n, w), rval_(rv), bmux_(mu)
+: NetAssign_(n, w), rval_(rv), bmux_(mu)
 {
-      for (unsigned idx = 0 ;  idx < pin_count() ;  idx += 1) {
-	    pin(idx).set_dir(NetObj::Link::OUTPUT);
-      }
-
       bool flag = rval_->set_width(1);
       if (flag == false) {
 	    cerr << rv->get_line() << ": Expression bit width" <<
@@ -1203,6 +1202,9 @@ NetNet* Design::find_signal(bool (*func)(const NetNet*))
 
 /*
  * $Log: netlist.cc,v $
+ * Revision 1.36  1999/06/13 16:30:06  steve
+ *  Unify the NetAssign constructors a bit.
+ *
  * Revision 1.35  1999/06/10 05:33:28  steve
  *  Handle a few more operator bit widths.
  *
diff --git a/netlist.h b/netlist.h
index 93f0481c1..2fd7e88cd 100644
--- a/netlist.h
+++ b/netlist.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: netlist.h,v 1.37 1999/06/09 03:00:06 steve Exp $"
+#ident "$Id: netlist.h,v 1.38 1999/06/13 16:30:06 steve Exp $"
 #endif
 
 /*
@@ -566,9 +566,17 @@ class NetProc {
  * appears as a procedural statement AND a structural node. The
  * LineInfo is the location of the assignment statement in the source.
  */
-class NetAssign  : public NetProc, public NetNode, public LineInfo {
+
+class NetAssign_ : public NetProc, public NetNode, public LineInfo {
+
+    protected:
+      NetAssign_(const string&n, unsigned w);
+      virtual ~NetAssign_() =0;
+};
+
+class NetAssign  : public NetAssign_ {
     public:
-      explicit NetAssign(Design*des, NetNet*lv, NetExpr*rv);
+      explicit NetAssign(const string&, Design*des, NetNet*lv, NetExpr*rv);
       ~NetAssign();
 
       const NetExpr*rval() const { return rval_; }
@@ -588,7 +596,7 @@ class NetAssign  : public NetProc, public NetNode, public LineInfo {
 /*
  * ... and this is a non-blocking version of above.
  */
-class NetAssignNB  : public NetProc, public NetNode, public LineInfo {
+class NetAssignNB  : public NetAssign_ {
     public:
       explicit NetAssignNB(const string&, Design*des, unsigned w, NetExpr*rv);
       explicit NetAssignNB(const string&, Design*des, unsigned w,
@@ -1237,6 +1245,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
 
 /*
  * $Log: netlist.h,v $
+ * Revision 1.38  1999/06/13 16:30:06  steve
+ *  Unify the NetAssign constructors a bit.
+ *
  * Revision 1.37  1999/06/09 03:00:06  steve
  *  Add support for procedural concatenation expression.
  *
diff --git a/t-verilog.cc b/t-verilog.cc
index 0b45e6da7..5ac6fd695 100644
--- a/t-verilog.cc
+++ b/t-verilog.cc
@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: t-verilog.cc,v 1.4 1999/05/01 02:57:53 steve Exp $"
+#ident "$Id: t-verilog.cc,v 1.5 1999/06/13 16:30:06 steve Exp $"
 #endif
 
 /*
@@ -43,7 +43,6 @@ class target_verilog : public target_t {
       virtual void logic(ostream&os, const NetLogic*);
       virtual void bufz(ostream&os, const NetBUFZ*);
       virtual void start_process(ostream&os, const NetProcTop*);
-      virtual void proc_assign(ostream&os, const NetAssign*);
       virtual void proc_block(ostream&os, const NetBlock*);
       virtual void proc_delay(ostream&os, const NetPDelay*);
       virtual void proc_event(ostream&os, const NetPEvent*);
@@ -152,32 +151,6 @@ void target_verilog::start_process(ostream&os, const NetProcTop*proc)
       indent_ = 6;
 }
 
-void target_verilog::proc_assign(ostream&os, const NetAssign*net)
-{
-      os << setw(indent_) << "";
-
-      const NetNet*lval;
-      unsigned msb, lsb;
-      net->find_lval_range(lval, msb, lsb);
-
-      if ((lsb == 0) && (msb == (lval->pin_count()-1))) {
-	    os << mangle(lval->name());
-
-      } else if (msb == lsb) {
-	    os << mangle(lval->name()) << "[" << msb << "]";
-
-      } else {
-	    os << mangle(lval->name()) << "[" << msb << ":" << lsb <<
-		  "]";
-      }
-
-      os << " = ";
-
-      emit_expr_(os, net->rval());
-
-      os  << ";" << endl;
-}
-
 void target_verilog::emit_expr_(ostream&os, const NetExpr*expr)
 {
 
@@ -298,6 +271,9 @@ const struct target tgt_verilog = {
 
 /*
  * $Log: t-verilog.cc,v $
+ * Revision 1.5  1999/06/13 16:30:06  steve
+ *  Unify the NetAssign constructors a bit.
+ *
  * Revision 1.4  1999/05/01 02:57:53  steve
  *  Handle much more complex event expressions.
  *