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Allow variable initialization in any scope. 

This is a SystemVerilog feature, so only allow it when
compiling SystemVerilog files.
This commit is contained in:
Stephen Williams 2012-03-11 15:08:42 -07:00
parent b0d61813b2
commit 5dbe688296
1 changed files with 2 additions and 2 deletions
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4
pform.cc
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@ -1864,8 +1864,8 @@ void pform_make_pgassign_list(list<PExpr*>*alist,
void pform_make_reginit(const struct vlltype&li, void pform_make_reginit(const struct vlltype&li,
perm_string name, PExpr*expr) perm_string name, PExpr*expr)
{ {
if (! pform_at_module_level()) { if (! pform_at_module_level() && !gn_system_verilog()) {
VLerror(li, "variable declaration assignments are only " VLerror(li, "error: variable declaration assignments are only "
"allowed at the module level."); "allowed at the module level.");
delete expr; delete expr;
return; return;