From 5dbe68829636b138b34ff4bda9c4b5a8b28ee5ab Mon Sep 17 00:00:00 2001
From: Stephen Williams <steve@icarus.com>
Date: Sun, 11 Mar 2012 15:08:42 -0700
Subject: [PATCH] Allow variable initialization in any scope.

This is a SystemVerilog feature, so only allow it when
compiling SystemVerilog files.
---
 pform.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/pform.cc b/pform.cc
index d34877855..d6acae6d4 100644
--- a/pform.cc
+++ b/pform.cc
@@ -1864,8 +1864,8 @@ void pform_make_pgassign_list(list<PExpr*>*alist,
 void pform_make_reginit(const struct vlltype&li,
 			perm_string name, PExpr*expr)
 {
-      if (! pform_at_module_level()) {
-	    VLerror(li, "variable declaration assignments are only "
+      if (! pform_at_module_level() && !gn_system_verilog()) {
+	    VLerror(li, "error: variable declaration assignments are only "
                         "allowed at the module level.");
 	    delete expr;
 	    return;