From 586e415d968ff30a6efad5dad5393056fe206c18 Mon Sep 17 00:00:00 2001
From: Martin Whitaker <icarus@martin-whitaker.me.uk>
Date: Sat, 27 Jun 2015 19:02:02 +0100
Subject: [PATCH] Allow macro arguments to be omitted when default values are
 available.

SystemVerilog allows fewer actual arguments than formal arguments when
all remaining formal arguments have default values.
---
 ivlpp/lexor.lex | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/ivlpp/lexor.lex b/ivlpp/lexor.lex
index b87eb0ae7..b22fac4cb 100644
--- a/ivlpp/lexor.lex
+++ b/ivlpp/lexor.lex
@@ -1379,11 +1379,22 @@ static void expand_using_args(void)
     int arg;
     int length;
 
-    if (def_argc != cur_macro->argc) {
+    if (def_argc > cur_macro->argc) {
         emit_pathline(istack);
-        fprintf(stderr, "error: wrong number of arguments for `%s\n", cur_macro->name);
+        fprintf(stderr, "error: too many arguments for `%s\n", cur_macro->name);
         return;
     }
+    while (def_argc < cur_macro->argc) {
+	if (cur_macro->defaults[def_argc]) {
+	    def_argl[def_argc] = 0;
+	    def_argc += 1;
+	    continue;
+	}
+        emit_pathline(istack);
+        fprintf(stderr, "error: too few arguments for `%s\n", cur_macro->name);
+        return;
+    }
+    assert(def_argc == cur_macro->argc);
 
     head = cur_macro->value;
     tail = head;