From 53284b95affcc654ab797b4922637efb38b299d6 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 11 Mar 2022 22:15:05 +0100 Subject: [PATCH] Allow to declare direction after data type for non-ANSI ports When using non-ANSI ports (System)Verilog allows to have separate declarations for the port direction and data type. E.g. ``` input x; reg x; ``` It is also allowed to first declare the data type and then the port type. E.g. ``` reg x; input x; ``` Currently this fails with an error message. Add support for handling this by allowing to change the port type of a signal from `NOT_A_PORT` to port direction. Signed-off-by: Lars-Peter Clausen --- PWire.cc | 4 +--- pform.cc | 8 +------- 2 files changed, 2 insertions(+), 10 deletions(-) diff --git a/PWire.cc b/PWire.cc index bf9b36954..5cba7ef97 100644 --- a/PWire.cc +++ b/PWire.cc @@ -98,12 +98,10 @@ bool PWire::set_port_type(NetNet::PortType pt) switch (port_type_) { case NetNet::PIMPLICIT: + case NetNet::NOT_A_PORT: port_type_ = pt; return true; - case NetNet::NOT_A_PORT: - return false; - default: if (port_type_ != pt) return false; diff --git a/pform.cc b/pform.cc index 374040291..8c211b1ef 100644 --- a/pform.cc +++ b/pform.cc @@ -3413,18 +3413,12 @@ static void pform_set_port_type(const struct vlltype&li, } switch (cur->get_port_type()) { + case NetNet::NOT_A_PORT: case NetNet::PIMPLICIT: if (! cur->set_port_type(pt)) VLerror("error setting port direction."); break; - case NetNet::NOT_A_PORT: - cerr << li << ": error: " - << "port " << name << " is not in the port list." - << endl; - error_count += 1; - break; - default: cerr << li << ": error: " << "port " << name << " already has a port declaration."