From 52a9fdde8a4bafec74e5fd4eb1c57ddd72a0a4d2 Mon Sep 17 00:00:00 2001
From: Stephen Williams <steve@icarus.com>
Date: Mon, 3 Feb 2014 19:22:59 -0800
Subject: [PATCH] Handle packed structs as module outputs.

---
 elab_lval.cc | 13 ++++++++-----
 parse.y      |  7 +++++++
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/elab_lval.cc b/elab_lval.cc
index d30c51bae..f5ab1320e 100644
--- a/elab_lval.cc
+++ b/elab_lval.cc
@@ -789,11 +789,14 @@ bool PEIdent::elaborate_lval_net_part_(Design*des,
       }
 
       if (reg->type()==NetNet::UNRESOLVED_WIRE) {
-	    cerr << get_fileline() << ": error: "
-		 << path_ << " Unable to part select unresolved wires."
-		 << endl;
-	    des->errors += 1;
-	    return false;
+	    bool rct = reg->test_and_set_part_driver(msb, lsb);
+	    if (rct) {
+		  cerr << get_fileline() << ": error: "
+		       << path_ << "Part select is double-driving unresolved wire."
+		       << endl;
+		  des->errors += 1;
+		  return false;
+	    }
       }
 
       const vector<netrange_t>&packed = reg->packed_dims();
diff --git a/parse.y b/parse.y
index aeb6c6007..8e34db037 100644
--- a/parse.y
+++ b/parse.y
@@ -3853,8 +3853,15 @@ port_declaration
 			  use_type = NetNet::IMPLICIT;
 		    else
 			  use_type = NetNet::IMPLICIT_REG;
+
+		      // The SystemVerilog types that can show up as
+		      // output ports are implicitly (on the inside)
+		      // variables because "reg" is not valid syntax
+		      // here.
 	      } else if (dynamic_cast<atom2_type_t*> ($4)) {
 		    use_type = NetNet::IMPLICIT_REG;
+	      } else if (dynamic_cast<struct_type_t*> ($4)) {
+		    use_type = NetNet::IMPLICIT_REG;
 	      }
 	}
 	ptmp = pform_module_port_reference(name, @2.text, @2.first_line);