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Add some logical operators.

This commit is contained in:
steve 1999-03-16 04:43:46 +00:00
parent b7f833dd71
commit 51b4f70c8f
2 changed files with 61 additions and 2 deletions
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13
vvm/vvm.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm.h,v 1.4 1999/02/08 03:55:55 steve Exp $" #ident "$Id: vvm.h,v 1.5 1999/03/16 04:43:46 steve Exp $"
#endif #endif
# include <vector> # include <vector>
@ -53,6 +53,14 @@ inline vvm_bit_t operator & (vvm_bit_t l, vvm_bit_t r)
return Vx; return Vx;
} }
inline vvm_bit_t operator | (vvm_bit_t l, vvm_bit_t r)
{
if (l == V1) return V1;
if (r == V1) return V1;
if ((l == V0) && (r == V0)) return V0;
return Vx;
}
inline vvm_bit_t operator ^ (vvm_bit_t l, vvm_bit_t r) inline vvm_bit_t operator ^ (vvm_bit_t l, vvm_bit_t r)
{ {
if (l == Vx) return Vx; if (l == Vx) return Vx;
@ -241,6 +249,9 @@ template <unsigned WIDTH> class vvm_signal_t : public vvm_monitor_t {
/* /*
* $Log: vvm.h,v $ * $Log: vvm.h,v $
* Revision 1.5 1999/03/16 04:43:46 steve
* Add some logical operators.
*
* Revision 1.4 1999/02/08 03:55:55 steve * Revision 1.4 1999/02/08 03:55:55 steve
* Do not generate code for signals, * Do not generate code for signals,
* instead use the NetESignal node to * instead use the NetESignal node to

50
vvm/vvm_func.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_func.h,v 1.2 1999/03/15 02:42:44 steve Exp $" #ident "$Id: vvm_func.h,v 1.3 1999/03/16 04:43:46 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
@ -45,6 +45,31 @@ vvm_bitset_t<WIDTH> vvm_unop_not(const vvm_bitset_t<WIDTH>&p)
return result; return result;
} }
/*
* The unary OR is the reduction OR. It returns a single bit.
*/
template <unsigned WIDTH>
vvm_bitset_t<1> vvm_unop_or(const vvm_bitset_t<WIDTH>&r)
{
vvm_bitset_t<1> res;
res[0] = V1;
for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) {
if (r[idx] == V1)
return res;
}
res[0] = V0;
return res;
}
template <unsigned WIDTH>
vvm_bitset_t<1> vvm_unop_lnot(const vvm_bitset_t<WIDTH>&r)
{
vvm_bitset_t<1> res = vvm_unop_or(r);
return vvm_unop_not(res);
}
/* /*
* Implement the binary AND operator. This is a bitwise and with all * Implement the binary AND operator. This is a bitwise and with all
* the parameters and the result having the same width. * the parameters and the result having the same width.
@ -193,8 +218,31 @@ vvm_bitset_t<1> vvm_binop_ne(const vvm_bitset_t<LW>&l,
return result; return result;
} }
template <unsigned LW, unsigned RW>
vvm_bitset_t<1> vvm_binop_land(const vvm_bitset_t<LW>&l,
const vvm_bitset_t<RW>&r)
{
vvm_bitset_t<1> res1 = vvm_unop_or(l);
vvm_bitset_t<1> res2 = vvm_unop_or(r);
res1[0] = res1[0] & res2[0];
return res1;
}
template <unsigned LW, unsigned RW>
vvm_bitset_t<1> vvm_binop_lor(const vvm_bitset_t<LW>&l,
const vvm_bitset_t<RW>&r)
{
vvm_bitset_t<1> res1 = vvm_unop_or(l);
vvm_bitset_t<1> res2 = vvm_unop_or(r);
res1[0] = res1[0] | res2[0];
return res1;
}
/* /*
* $Log: vvm_func.h,v $ * $Log: vvm_func.h,v $
* Revision 1.3 1999/03/16 04:43:46 steve
* Add some logical operators.
*
* Revision 1.2 1999/03/15 02:42:44 steve * Revision 1.2 1999/03/15 02:42:44 steve
* Add the AND and OR bitwise operators. * Add the AND and OR bitwise operators.
* *