From 51b4f70c8f1d3e99a85792ea6a7c34d7ea18c885 Mon Sep 17 00:00:00 2001
From: steve <steve>
Date: Tue, 16 Mar 1999 04:43:46 +0000
Subject: [PATCH]  Add some logical operators.

---
 vvm/vvm.h      | 13 ++++++++++++-
 vvm/vvm_func.h | 50 +++++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 61 insertions(+), 2 deletions(-)

diff --git a/vvm/vvm.h b/vvm/vvm.h
index 2ec0158be..41bfde4d3 100644
--- a/vvm/vvm.h
+++ b/vvm/vvm.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: vvm.h,v 1.4 1999/02/08 03:55:55 steve Exp $"
+#ident "$Id: vvm.h,v 1.5 1999/03/16 04:43:46 steve Exp $"
 #endif
 
 # include  <vector>
@@ -53,6 +53,14 @@ inline vvm_bit_t operator & (vvm_bit_t l, vvm_bit_t r)
       return Vx;
 }
 
+inline vvm_bit_t operator | (vvm_bit_t l, vvm_bit_t r)
+{
+      if (l == V1) return V1;
+      if (r == V1) return V1;
+      if ((l == V0) && (r == V0)) return V0;
+      return Vx;
+}
+
 inline vvm_bit_t operator ^ (vvm_bit_t l, vvm_bit_t r)
 {
       if (l == Vx) return Vx;
@@ -241,6 +249,9 @@ template <unsigned WIDTH> class vvm_signal_t  : public vvm_monitor_t {
 
 /*
  * $Log: vvm.h,v $
+ * Revision 1.5  1999/03/16 04:43:46  steve
+ *  Add some logical operators.
+ *
  * Revision 1.4  1999/02/08 03:55:55  steve
  *  Do not generate code for signals,
  *  instead use the NetESignal node to
diff --git a/vvm/vvm_func.h b/vvm/vvm_func.h
index 5b806cdd8..68415f2a3 100644
--- a/vvm/vvm_func.h
+++ b/vvm/vvm_func.h
@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: vvm_func.h,v 1.2 1999/03/15 02:42:44 steve Exp $"
+#ident "$Id: vvm_func.h,v 1.3 1999/03/16 04:43:46 steve Exp $"
 #endif
 
 # include  "vvm.h"
@@ -45,6 +45,31 @@ vvm_bitset_t<WIDTH> vvm_unop_not(const vvm_bitset_t<WIDTH>&p)
       return result;
 }
 
+/*
+ * The unary OR is the reduction OR. It returns a single bit.
+ */
+template <unsigned WIDTH>
+vvm_bitset_t<1> vvm_unop_or(const vvm_bitset_t<WIDTH>&r)
+{
+      vvm_bitset_t<1> res;
+      res[0] = V1;
+
+      for (unsigned idx = 0 ;  idx < WIDTH ;  idx += 1) {
+	    if (r[idx] == V1)
+		  return res;
+      }
+
+      res[0] = V0;
+      return res;
+}
+
+template <unsigned WIDTH>
+vvm_bitset_t<1> vvm_unop_lnot(const vvm_bitset_t<WIDTH>&r)
+{
+      vvm_bitset_t<1> res = vvm_unop_or(r);
+      return vvm_unop_not(res);
+}
+
 /*
  * Implement the binary AND operator. This is a bitwise and with all
  * the parameters and the result having the same width.
@@ -193,8 +218,31 @@ vvm_bitset_t<1> vvm_binop_ne(const vvm_bitset_t<LW>&l,
       return result;
 }
 
+template <unsigned LW, unsigned RW>
+vvm_bitset_t<1> vvm_binop_land(const vvm_bitset_t<LW>&l,
+			       const vvm_bitset_t<RW>&r)
+{
+      vvm_bitset_t<1> res1 = vvm_unop_or(l);
+      vvm_bitset_t<1> res2 = vvm_unop_or(r);
+      res1[0] = res1[0] & res2[0];
+      return res1;
+}
+
+template <unsigned LW, unsigned RW>
+vvm_bitset_t<1> vvm_binop_lor(const vvm_bitset_t<LW>&l,
+			       const vvm_bitset_t<RW>&r)
+{
+      vvm_bitset_t<1> res1 = vvm_unop_or(l);
+      vvm_bitset_t<1> res2 = vvm_unop_or(r);
+      res1[0] = res1[0] | res2[0];
+      return res1;
+}
+
 /*
  * $Log: vvm_func.h,v $
+ * Revision 1.3  1999/03/16 04:43:46  steve
+ *  Add some logical operators.
+ *
  * Revision 1.2  1999/03/15 02:42:44  steve
  *  Add the AND and OR bitwise operators.
  *