Realign generation flags to correspond to IEEE1364 nomenclature.
IEEE1364 has specific names for the various generations of Verilog that are supported. Icarus Verilog should stick to those names for selection the language feature set. In the process, the extensions that were tied to the 2x generations are pulled out out and given their own enable flags. The makes all the feature control more regular and understandable.
This commit is contained in:
parent
3a8a6976e1
commit
3a61b94e98
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@ -100,23 +100,22 @@ extern int build_library_index(const char*path, bool key_case_sensitive);
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enum generation_t {
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enum generation_t {
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GN_VER1995 = 1,
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GN_VER1995 = 1,
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GN_VER2001 = 2,
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GN_VER2001 = 2,
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GN_VER2001X = 3,
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GN_VER2005 = 3,
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GN_DEFAULT = 3
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GN_DEFAULT = 3
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};
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};
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extern generation_t generation_flag;
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extern generation_t generation_flag;
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/* If this flag is true, enable extended types support. */
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extern bool gn_cadence_types_flag;
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extern bool gn_cadence_types_flag;
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/* These functions test that specific features are enabled. */
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/* If this flag is true, enable miscellaneous extensions. */
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inline bool gn_cadence_types_enabled()
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extern bool gn_icarus_misc_flag;
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{ return gn_cadence_types_flag && generation_flag==GN_VER2001X; }
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/* If this flag is true, then elaborate specify blocks. If this flag
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/* If this flag is true, then elaborate specify blocks. If this flag
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is false, then skip elaboration of specify behavior. */
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is false, then skip elaboration of specify behavior. */
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extern bool gn_specify_blocks_flag;
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extern bool gn_specify_blocks_flag;
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/* If this flag is true, then support/elaborate Verilog-AMS. */
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/* If this flag is true, then support/elaborate Verilog-AMS. */
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extern bool gn_verilog_ams_flag;
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extern bool gn_verilog_ams_flag;
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@ -5,7 +5,7 @@ iverilog - Icarus Verilog compiler
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.SH SYNOPSIS
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.SH SYNOPSIS
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.B iverilog
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.B iverilog
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[-ESVv] [-Bpath] [-ccmdfile|-fcmdfile] [-Dmacro[=defn]] [-pflag=value]
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[-ESVv] [-Bpath] [-ccmdfile|-fcmdfile] [-Dmacro[=defn]] [-pflag=value]
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[-dname] [-g1|-g2|-g2x|-gspecify|-gxtypes|-gio-range-error]
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[-dname] [-g1995|-g2001|-g2005|-g<feature>]
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[-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutputfilename]
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[-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutputfilename]
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[-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath] sourcefile
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[-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath] sourcefile
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@ -55,15 +55,18 @@ is the Verilog input, but with file inclusions and macro references
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expanded and removed. This is useful, for example, to preprocess
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expanded and removed. This is useful, for example, to preprocess
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Verilog source for use by other compilers.
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Verilog source for use by other compilers.
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.TP 8
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.TP 8
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.B -g1\fI|\fP-g2\fI|\fP-g2x
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.B -g1995\fI|\fP-g2001\fI|\fP-g2005
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Select the Verilog language \fIgeneration\fP to support in the
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Select the Verilog language \fIgeneration\fP to support in the
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compiler. This selects between \fIIEEE1364-1995\fP(1),
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compiler. This selects between \fIIEEE1364-1995\fP,
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\fIIEEE1364-2001\fP(2), or \fIVerilog with extension\fP(2x). Normally,
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\fIIEEE1364-2001\fP(2), or \fIIEEE1364-2005\fP. Normally,
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Icarus Verilog defaults to the latest known generation of the
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Icarus Verilog defaults to the latest known generation of the
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language. This flag is most useful to restrict the language to a set
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language. This flag is most useful to restrict the language to a set
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supported by tools of specific generations, for compatibility with
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supported by tools of specific generations, for compatibility with
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other tools.
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other tools.
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.TP 8
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.TP 8
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.B -gverilog-ams\fI|-fP-gno-verilog-ams
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Enable or disable (default) support for Verilog-AMS.
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.TP 8
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.B -gspecify\fI|\fP-gno-specify
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.B -gspecify\fI|\fP-gno-specify
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Enable (default) or disable specify block support. When enabled,
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Enable (default) or disable specify block support. When enabled,
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specify block code is elaborated. When disabled, specify blocks are
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specify block code is elaborated. When disabled, specify blocks are
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@ -109,6 +109,7 @@ const char*depfile = 0;
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const char*generation = "2x";
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const char*generation = "2x";
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const char*gen_specify = "specify";
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const char*gen_specify = "specify";
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const char*gen_xtypes = "xtypes";
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const char*gen_xtypes = "xtypes";
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const char*gen_icarus = "icarus-misc";
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const char*gen_io_range_error = "io-range-error";
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const char*gen_io_range_error = "io-range-error";
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const char*gen_verilog_ams = "no-verilog-ams";
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const char*gen_verilog_ams = "no-verilog-ams";
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@ -431,21 +432,42 @@ void process_file_name(const char*name, int lib_flag)
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int process_generation(const char*name)
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int process_generation(const char*name)
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{
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{
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if (strcmp(name,"1") == 0)
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if (strcmp(name,"1995") == 0)
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generation = "1";
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generation = "1995";
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else if (strcmp(name,"2") == 0)
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else if (strcmp(name,"2001") == 0)
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generation = "2";
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generation = "2001";
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else if (strcmp(name,"2x") == 0)
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else if (strcmp(name,"2005") == 0)
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generation = "2x";
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generation = "2005";
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else if (strcmp(name,"xtypes") == 0)
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else if (strcmp(name,"1") == 0) { /* Deprecated: use 1995 */
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generation = "1995";
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gen_xtypes = "no-xtypes";
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gen_icarus = "no-icarus-misc";
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} else if (strcmp(name,"2") == 0) { /* Deprecated: use 2001 */
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generation = "2001";
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gen_xtypes = "no-xtypes";
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gen_icarus = "no-icarus-misc";
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} else if (strcmp(name,"2x") == 0) { /* Deprecated: use 2005/xtypes */
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generation = "2005";
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gen_xtypes = "xtypes";
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gen_icarus = "icarus-misc";
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} else if (strcmp(name,"xtypes") == 0)
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gen_xtypes = "xtypes";
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gen_xtypes = "xtypes";
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else if (strcmp(name,"no-xtypes") == 0)
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else if (strcmp(name,"no-xtypes") == 0)
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gen_xtypes = "no-xtypes";
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gen_xtypes = "no-xtypes";
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else if (strcmp(name,"icarus-misc") == 0)
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gen_icarus = "icarus-misc";
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else if (strcmp(name,"no-icarus-misc") == 0)
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gen_icarus = "no-icarus-misc";
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else if (strcmp(name,"specify") == 0)
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else if (strcmp(name,"specify") == 0)
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gen_specify = "specify";
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gen_specify = "specify";
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@ -474,13 +496,15 @@ int process_generation(const char*name)
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fprintf(stderr, "Unknown/Unsupported Language generation "
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fprintf(stderr, "Unknown/Unsupported Language generation "
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"%s\n\n", name);
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"%s\n\n", name);
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fprintf(stderr, "Supported generations are:\n");
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fprintf(stderr, "Supported generations are:\n");
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fprintf(stderr, " 1 -- IEEE1364-1995 (Verilog 1)\n"
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fprintf(stderr, " 1995 -- IEEE1364-1995\n"
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" 2 -- IEEE1364-2001 (Verilog 2001)\n"
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" 2001 -- IEEE1364-2001\n"
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" 2x -- Verilog with extensions\n"
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" 2005 -- IEEE1364-2005\n"
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"Other generation flags:\n"
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"Other generation flags:\n"
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" specify | no-specify\n"
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" specify | no-specify\n"
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" verilog-ams | no-verinlog-ams\n"
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" std-include | no-std-include\n"
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" std-include | no-std-include\n"
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" xtypes | no-xtypes\n"
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" xtypes | no-xtypes\n"
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" icarus-misc | no-icarus-misc\n"
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" io-range-error | no-io-range-error\n");
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" io-range-error | no-io-range-error\n");
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return 1;
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return 1;
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}
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}
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@ -747,6 +771,7 @@ int main(int argc, char **argv)
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fprintf(iconfig_file, "generation:%s\n", gen_xtypes);
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fprintf(iconfig_file, "generation:%s\n", gen_xtypes);
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fprintf(iconfig_file, "generation:%s\n", gen_io_range_error);
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fprintf(iconfig_file, "generation:%s\n", gen_io_range_error);
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fprintf(iconfig_file, "generation:%s\n", gen_verilog_ams);
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fprintf(iconfig_file, "generation:%s\n", gen_verilog_ams);
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fprintf(iconfig_file, "generation:%s\n", gen_icarus);
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fprintf(iconfig_file, "warnings:%s\n", warning_flags);
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fprintf(iconfig_file, "warnings:%s\n", warning_flags);
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fprintf(iconfig_file, "out:%s\n", opath);
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fprintf(iconfig_file, "out:%s\n", opath);
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if (depfile) fprintf(iconfig_file, "depfile:%s\n", depfile);
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if (depfile) fprintf(iconfig_file, "depfile:%s\n", depfile);
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@ -187,7 +187,7 @@ NetExpr* PEBinary::elaborate_expr_base_(Design*des,
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/* The % operator does not support real arguments in
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/* The % operator does not support real arguments in
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baseline Verilog. But we allow it in our extended
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baseline Verilog. But we allow it in our extended
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form of Verilog. */
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form of Verilog. */
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if (generation_flag < GN_VER2001X) {
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if (! gn_icarus_misc_flag) {
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if (lp->expr_type()==IVL_VT_REAL ||
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if (lp->expr_type()==IVL_VT_REAL ||
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rp->expr_type()==IVL_VT_REAL) {
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rp->expr_type()==IVL_VT_REAL) {
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cerr << get_fileline() << ": error: Modulus operator "
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cerr << get_fileline() << ": error: Modulus operator "
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@ -808,7 +808,7 @@ NetNet* PEBinary::elaborate_net_mod_(Design*des, NetScope*scope,
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/* The % operator does not support real arguments in baseline
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/* The % operator does not support real arguments in baseline
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Verilog. But we allow it in our extended form of Verilog. */
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Verilog. But we allow it in our extended form of Verilog. */
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if (generation_flag < GN_VER2001X && lsig->data_type() == IVL_VT_REAL) {
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if (gn_icarus_misc_flag==false && lsig->data_type() == IVL_VT_REAL) {
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cerr << get_fileline() << ": error: Modulus operator may not "
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cerr << get_fileline() << ": error: Modulus operator may not "
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"have REAL operands." << endl;
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"have REAL operands." << endl;
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des->errors += 1;
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des->errors += 1;
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@ -323,7 +323,7 @@ bool PGAssign::elaborate_sig(Design*des, NetScope*scope) const
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to implicitly declare nets. However, so many tools do allow
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to implicitly declare nets. However, so many tools do allow
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it that Icarus Verilog will allow it, at least if extensions
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it that Icarus Verilog will allow it, at least if extensions
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are enabled. */
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are enabled. */
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if (generation_flag == GN_VER2001X)
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if (gn_icarus_misc_flag)
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return pin(0)->elaborate_sig(des, scope);
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return pin(0)->elaborate_sig(des, scope);
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return true;
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return true;
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@ -438,7 +438,7 @@ NetNet* NetEBDiv::synthesize(Design*des)
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case '%': {
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case '%': {
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/* Baseline Verilog does not support the % operator with
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/* Baseline Verilog does not support the % operator with
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real arguments, but we allow it in our extended form. */
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real arguments, but we allow it in our extended form. */
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if (real_args && generation_flag < GN_VER2001X) {
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if (real_args && !gn_icarus_misc_flag) {
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cerr << get_fileline() << ": error: Modulus operator "
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cerr << get_fileline() << ": error: Modulus operator "
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"may not have REAL operands." << endl;
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"may not have REAL operands." << endl;
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des->errors += 1;
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des->errors += 1;
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11
lexor.lex
11
lexor.lex
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@ -218,17 +218,6 @@ W [ \t\b\f\r]+
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rc = PATHPULSE_IDENTIFIER;
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rc = PATHPULSE_IDENTIFIER;
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break;
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break;
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case K_bool:
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case K_logic:
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case K_wone:
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if (! gn_cadence_types_enabled()) {
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yylval.text = strdupnew(yytext);
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rc = IDENTIFIER;
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} else {
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yylval.text = 0;
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}
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break;
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case K_edge:
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case K_edge:
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BEGIN(EDGES);
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BEGIN(EDGES);
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break;
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break;
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40
main.cc
40
main.cc
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@ -85,6 +85,7 @@ const char*target = "null";
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* is a major mode, and the gn_* flags control specific sub-features.
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* is a major mode, and the gn_* flags control specific sub-features.
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*/
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*/
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generation_t generation_flag = GN_DEFAULT;
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generation_t generation_flag = GN_DEFAULT;
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bool gn_icarus_misc_flag = true;
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bool gn_cadence_types_flag = true;
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bool gn_cadence_types_flag = true;
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bool gn_specify_blocks_flag = true;
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bool gn_specify_blocks_flag = true;
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bool gn_io_range_error_flag = true;
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bool gn_io_range_error_flag = true;
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@ -198,14 +199,30 @@ const char *net_func_to_name(const net_func func)
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static void process_generation_flag(const char*gen)
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static void process_generation_flag(const char*gen)
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{
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{
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if (strcmp(gen,"1") == 0) {
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if (strcmp(gen,"1") == 0) { // FIXME: Deprecated for 1995
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generation_flag = GN_VER1995;
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generation_flag = GN_VER1995;
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} else if (strcmp(gen,"2") == 0) {
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} else if (strcmp(gen,"2") == 0) { // FIXME: Deprecated for 2001
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generation_flag = GN_VER2001;
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generation_flag = GN_VER2001;
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} else if (strcmp(gen,"2x") == 0) {
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} else if (strcmp(gen,"2x") == 0) { // FIXME: Deprecated for 2001
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generation_flag = GN_VER2001X;
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generation_flag = GN_VER2001;
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gn_icarus_misc_flag = true;
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} else if (strcmp(gen,"1995") == 0) {
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generation_flag = GN_VER1995;
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} else if (strcmp(gen,"2001") == 0) {
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generation_flag = GN_VER2001;
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} else if (strcmp(gen,"2005") == 0) {
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generation_flag = GN_VER2005;
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} else if (strcmp(gen,"icarus-misc") == 0) {
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gn_icarus_misc_flag = true;
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} else if (strcmp(gen,"no-icarus-misc") == 0) {
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gn_icarus_misc_flag = false;
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} else if (strcmp(gen,"xtypes") == 0) {
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} else if (strcmp(gen,"xtypes") == 0) {
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gn_cadence_types_flag = true;
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gn_cadence_types_flag = true;
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@ -609,15 +626,15 @@ int main(int argc, char*argv[])
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lexor_keyword_mask |= GN_KEYWORDS_1364_2001;
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lexor_keyword_mask |= GN_KEYWORDS_1364_2001;
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lexor_keyword_mask |= GN_KEYWORDS_1364_2001_CONFIG;
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lexor_keyword_mask |= GN_KEYWORDS_1364_2001_CONFIG;
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break;
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break;
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case GN_VER2001X:
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case GN_VER2005:
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lexor_keyword_mask |= GN_KEYWORDS_1364_1995;
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lexor_keyword_mask |= GN_KEYWORDS_1364_1995;
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lexor_keyword_mask |= GN_KEYWORDS_1364_2001;
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lexor_keyword_mask |= GN_KEYWORDS_1364_2001;
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lexor_keyword_mask |= GN_KEYWORDS_1364_2001_CONFIG;
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lexor_keyword_mask |= GN_KEYWORDS_1364_2001_CONFIG;
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lexor_keyword_mask |= GN_KEYWORDS_ICARUS;
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lexor_keyword_mask |= GN_KEYWORDS_1364_2005;
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break;
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break;
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}
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}
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if (gn_cadence_types_enabled())
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if (gn_cadence_types_flag)
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lexor_keyword_mask |= GN_KEYWORDS_ICARUS;
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lexor_keyword_mask |= GN_KEYWORDS_ICARUS;
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if (gn_verilog_ams_flag)
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if (gn_verilog_ams_flag)
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@ -635,8 +652,8 @@ int main(int argc, char*argv[])
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case GN_VER2001:
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case GN_VER2001:
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cout << "IEEE1364-2001";
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cout << "IEEE1364-2001";
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break;
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break;
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case GN_VER2001X:
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case GN_VER2005:
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cout << "IEEE1364-2001+Extensions";
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cout << "IEEE1364-2005";
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break;
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break;
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}
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}
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@ -653,6 +670,11 @@ int main(int argc, char*argv[])
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else
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else
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cout << ",no-xtypes";
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cout << ",no-xtypes";
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if (gn_icarus_misc_flag)
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cout << ",icarus-misc";
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else
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cout << ",no-icarus-misc";
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cout << endl << "PARSING INPUT" << endl;
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cout << endl << "PARSING INPUT" << endl;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue