From 3a61b94e98b49f13462a0d27e27f20c4d93aeab8 Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Wed, 7 May 2008 17:46:56 -0700 Subject: [PATCH] Realign generation flags to correspond to IEEE1364 nomenclature. IEEE1364 has specific names for the various generations of Verilog that are supported. Icarus Verilog should stick to those names for selection the language feature set. In the process, the extensions that were tied to the 2x generations are pulled out out and given their own enable flags. The makes all the feature control more regular and understandable. --- compiler.h | 9 ++++----- driver/iverilog.man | 11 +++++++---- driver/main.c | 45 +++++++++++++++++++++++++++++++++++---------- elab_expr.cc | 2 +- elab_net.cc | 2 +- elab_sig.cc | 2 +- expr_synth.cc | 2 +- lexor.lex | 11 ----------- main.cc | 40 +++++++++++++++++++++++++++++++--------- 9 files changed, 81 insertions(+), 43 deletions(-) diff --git a/compiler.h b/compiler.h index 66adf8865..6b654e6e2 100644 --- a/compiler.h +++ b/compiler.h @@ -100,23 +100,22 @@ extern int build_library_index(const char*path, bool key_case_sensitive); enum generation_t { GN_VER1995 = 1, GN_VER2001 = 2, - GN_VER2001X = 3, + GN_VER2005 = 3, GN_DEFAULT = 3 }; extern generation_t generation_flag; +/* If this flag is true, enable extended types support. */ extern bool gn_cadence_types_flag; -/* These functions test that specific features are enabled. */ -inline bool gn_cadence_types_enabled() -{ return gn_cadence_types_flag && generation_flag==GN_VER2001X; } +/* If this flag is true, enable miscellaneous extensions. */ +extern bool gn_icarus_misc_flag; /* If this flag is true, then elaborate specify blocks. If this flag is false, then skip elaboration of specify behavior. */ extern bool gn_specify_blocks_flag; - /* If this flag is true, then support/elaborate Verilog-AMS. */ extern bool gn_verilog_ams_flag; diff --git a/driver/iverilog.man b/driver/iverilog.man index 8c1356e97..dde5b0812 100644 --- a/driver/iverilog.man +++ b/driver/iverilog.man @@ -5,7 +5,7 @@ iverilog - Icarus Verilog compiler .SH SYNOPSIS .B iverilog [-ESVv] [-Bpath] [-ccmdfile|-fcmdfile] [-Dmacro[=defn]] [-pflag=value] -[-dname] [-g1|-g2|-g2x|-gspecify|-gxtypes|-gio-range-error] +[-dname] [-g1995|-g2001|-g2005|-g] [-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutputfilename] [-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath] sourcefile @@ -55,15 +55,18 @@ is the Verilog input, but with file inclusions and macro references expanded and removed. This is useful, for example, to preprocess Verilog source for use by other compilers. .TP 8 -.B -g1\fI|\fP-g2\fI|\fP-g2x +.B -g1995\fI|\fP-g2001\fI|\fP-g2005 Select the Verilog language \fIgeneration\fP to support in the -compiler. This selects between \fIIEEE1364-1995\fP(1), -\fIIEEE1364-2001\fP(2), or \fIVerilog with extension\fP(2x). Normally, +compiler. This selects between \fIIEEE1364-1995\fP, +\fIIEEE1364-2001\fP(2), or \fIIEEE1364-2005\fP. Normally, Icarus Verilog defaults to the latest known generation of the language. This flag is most useful to restrict the language to a set supported by tools of specific generations, for compatibility with other tools. .TP 8 +.B -gverilog-ams\fI|-fP-gno-verilog-ams +Enable or disable (default) support for Verilog-AMS. +.TP 8 .B -gspecify\fI|\fP-gno-specify Enable (default) or disable specify block support. When enabled, specify block code is elaborated. When disabled, specify blocks are diff --git a/driver/main.c b/driver/main.c index 953262012..b11bf9494 100644 --- a/driver/main.c +++ b/driver/main.c @@ -109,6 +109,7 @@ const char*depfile = 0; const char*generation = "2x"; const char*gen_specify = "specify"; const char*gen_xtypes = "xtypes"; +const char*gen_icarus = "icarus-misc"; const char*gen_io_range_error = "io-range-error"; const char*gen_verilog_ams = "no-verilog-ams"; @@ -431,21 +432,42 @@ void process_file_name(const char*name, int lib_flag) int process_generation(const char*name) { - if (strcmp(name,"1") == 0) - generation = "1"; + if (strcmp(name,"1995") == 0) + generation = "1995"; - else if (strcmp(name,"2") == 0) - generation = "2"; + else if (strcmp(name,"2001") == 0) + generation = "2001"; - else if (strcmp(name,"2x") == 0) - generation = "2x"; + else if (strcmp(name,"2005") == 0) + generation = "2005"; - else if (strcmp(name,"xtypes") == 0) + else if (strcmp(name,"1") == 0) { /* Deprecated: use 1995 */ + generation = "1995"; + gen_xtypes = "no-xtypes"; + gen_icarus = "no-icarus-misc"; + + } else if (strcmp(name,"2") == 0) { /* Deprecated: use 2001 */ + generation = "2001"; + gen_xtypes = "no-xtypes"; + gen_icarus = "no-icarus-misc"; + + } else if (strcmp(name,"2x") == 0) { /* Deprecated: use 2005/xtypes */ + generation = "2005"; + gen_xtypes = "xtypes"; + gen_icarus = "icarus-misc"; + + } else if (strcmp(name,"xtypes") == 0) gen_xtypes = "xtypes"; else if (strcmp(name,"no-xtypes") == 0) gen_xtypes = "no-xtypes"; + else if (strcmp(name,"icarus-misc") == 0) + gen_icarus = "icarus-misc"; + + else if (strcmp(name,"no-icarus-misc") == 0) + gen_icarus = "no-icarus-misc"; + else if (strcmp(name,"specify") == 0) gen_specify = "specify"; @@ -474,13 +496,15 @@ int process_generation(const char*name) fprintf(stderr, "Unknown/Unsupported Language generation " "%s\n\n", name); fprintf(stderr, "Supported generations are:\n"); - fprintf(stderr, " 1 -- IEEE1364-1995 (Verilog 1)\n" - " 2 -- IEEE1364-2001 (Verilog 2001)\n" - " 2x -- Verilog with extensions\n" + fprintf(stderr, " 1995 -- IEEE1364-1995\n" + " 2001 -- IEEE1364-2001\n" + " 2005 -- IEEE1364-2005\n" "Other generation flags:\n" " specify | no-specify\n" + " verilog-ams | no-verinlog-ams\n" " std-include | no-std-include\n" " xtypes | no-xtypes\n" + " icarus-misc | no-icarus-misc\n" " io-range-error | no-io-range-error\n"); return 1; } @@ -747,6 +771,7 @@ int main(int argc, char **argv) fprintf(iconfig_file, "generation:%s\n", gen_xtypes); fprintf(iconfig_file, "generation:%s\n", gen_io_range_error); fprintf(iconfig_file, "generation:%s\n", gen_verilog_ams); + fprintf(iconfig_file, "generation:%s\n", gen_icarus); fprintf(iconfig_file, "warnings:%s\n", warning_flags); fprintf(iconfig_file, "out:%s\n", opath); if (depfile) fprintf(iconfig_file, "depfile:%s\n", depfile); diff --git a/elab_expr.cc b/elab_expr.cc index 4a024df34..8d1845a04 100644 --- a/elab_expr.cc +++ b/elab_expr.cc @@ -187,7 +187,7 @@ NetExpr* PEBinary::elaborate_expr_base_(Design*des, /* The % operator does not support real arguments in baseline Verilog. But we allow it in our extended form of Verilog. */ - if (generation_flag < GN_VER2001X) { + if (! gn_icarus_misc_flag) { if (lp->expr_type()==IVL_VT_REAL || rp->expr_type()==IVL_VT_REAL) { cerr << get_fileline() << ": error: Modulus operator " diff --git a/elab_net.cc b/elab_net.cc index fa57850db..a1446b9c6 100644 --- a/elab_net.cc +++ b/elab_net.cc @@ -808,7 +808,7 @@ NetNet* PEBinary::elaborate_net_mod_(Design*des, NetScope*scope, /* The % operator does not support real arguments in baseline Verilog. But we allow it in our extended form of Verilog. */ - if (generation_flag < GN_VER2001X && lsig->data_type() == IVL_VT_REAL) { + if (gn_icarus_misc_flag==false && lsig->data_type() == IVL_VT_REAL) { cerr << get_fileline() << ": error: Modulus operator may not " "have REAL operands." << endl; des->errors += 1; diff --git a/elab_sig.cc b/elab_sig.cc index 7c73c718d..9878c902a 100644 --- a/elab_sig.cc +++ b/elab_sig.cc @@ -323,7 +323,7 @@ bool PGAssign::elaborate_sig(Design*des, NetScope*scope) const to implicitly declare nets. However, so many tools do allow it that Icarus Verilog will allow it, at least if extensions are enabled. */ - if (generation_flag == GN_VER2001X) + if (gn_icarus_misc_flag) return pin(0)->elaborate_sig(des, scope); return true; diff --git a/expr_synth.cc b/expr_synth.cc index 483dfea28..3f079fc5c 100644 --- a/expr_synth.cc +++ b/expr_synth.cc @@ -438,7 +438,7 @@ NetNet* NetEBDiv::synthesize(Design*des) case '%': { /* Baseline Verilog does not support the % operator with real arguments, but we allow it in our extended form. */ - if (real_args && generation_flag < GN_VER2001X) { + if (real_args && !gn_icarus_misc_flag) { cerr << get_fileline() << ": error: Modulus operator " "may not have REAL operands." << endl; des->errors += 1; diff --git a/lexor.lex b/lexor.lex index 87dffe885..2dd5efcf4 100644 --- a/lexor.lex +++ b/lexor.lex @@ -218,17 +218,6 @@ W [ \t\b\f\r]+ rc = PATHPULSE_IDENTIFIER; break; - case K_bool: - case K_logic: - case K_wone: - if (! gn_cadence_types_enabled()) { - yylval.text = strdupnew(yytext); - rc = IDENTIFIER; - } else { - yylval.text = 0; - } - break; - case K_edge: BEGIN(EDGES); break; diff --git a/main.cc b/main.cc index 7c42367ad..6e6bcfb25 100644 --- a/main.cc +++ b/main.cc @@ -85,6 +85,7 @@ const char*target = "null"; * is a major mode, and the gn_* flags control specific sub-features. */ generation_t generation_flag = GN_DEFAULT; +bool gn_icarus_misc_flag = true; bool gn_cadence_types_flag = true; bool gn_specify_blocks_flag = true; bool gn_io_range_error_flag = true; @@ -198,14 +199,30 @@ const char *net_func_to_name(const net_func func) static void process_generation_flag(const char*gen) { - if (strcmp(gen,"1") == 0) { + if (strcmp(gen,"1") == 0) { // FIXME: Deprecated for 1995 generation_flag = GN_VER1995; - } else if (strcmp(gen,"2") == 0) { + } else if (strcmp(gen,"2") == 0) { // FIXME: Deprecated for 2001 generation_flag = GN_VER2001; - } else if (strcmp(gen,"2x") == 0) { - generation_flag = GN_VER2001X; + } else if (strcmp(gen,"2x") == 0) { // FIXME: Deprecated for 2001 + generation_flag = GN_VER2001; + gn_icarus_misc_flag = true; + + } else if (strcmp(gen,"1995") == 0) { + generation_flag = GN_VER1995; + + } else if (strcmp(gen,"2001") == 0) { + generation_flag = GN_VER2001; + + } else if (strcmp(gen,"2005") == 0) { + generation_flag = GN_VER2005; + + } else if (strcmp(gen,"icarus-misc") == 0) { + gn_icarus_misc_flag = true; + + } else if (strcmp(gen,"no-icarus-misc") == 0) { + gn_icarus_misc_flag = false; } else if (strcmp(gen,"xtypes") == 0) { gn_cadence_types_flag = true; @@ -609,15 +626,15 @@ int main(int argc, char*argv[]) lexor_keyword_mask |= GN_KEYWORDS_1364_2001; lexor_keyword_mask |= GN_KEYWORDS_1364_2001_CONFIG; break; - case GN_VER2001X: + case GN_VER2005: lexor_keyword_mask |= GN_KEYWORDS_1364_1995; lexor_keyword_mask |= GN_KEYWORDS_1364_2001; lexor_keyword_mask |= GN_KEYWORDS_1364_2001_CONFIG; - lexor_keyword_mask |= GN_KEYWORDS_ICARUS; + lexor_keyword_mask |= GN_KEYWORDS_1364_2005; break; } - if (gn_cadence_types_enabled()) + if (gn_cadence_types_flag) lexor_keyword_mask |= GN_KEYWORDS_ICARUS; if (gn_verilog_ams_flag) @@ -635,8 +652,8 @@ int main(int argc, char*argv[]) case GN_VER2001: cout << "IEEE1364-2001"; break; - case GN_VER2001X: - cout << "IEEE1364-2001+Extensions"; + case GN_VER2005: + cout << "IEEE1364-2005"; break; } @@ -653,6 +670,11 @@ int main(int argc, char*argv[]) else cout << ",no-xtypes"; + if (gn_icarus_misc_flag) + cout << ",icarus-misc"; + else + cout << ",no-icarus-misc"; + cout << endl << "PARSING INPUT" << endl; }