From 3939126625db144207551593f8d9603253c6ac87 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Fri, 11 Mar 2022 21:24:17 +0100
Subject: [PATCH] Handle empty class item declarations in parser

The SystemVerilog grammar explicitly allows an empty class item
declaration. The empty class item declaration is just a semicolon and has
no effect.

E.g. the following is legal
```
class C
  int x;;;
endclass
```

Add support to the parser to accept empty class item declarations.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 parse.y | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/parse.y b/parse.y
index 50d5e62b0..9ac90a9fd 100644
--- a/parse.y
+++ b/parse.y
@@ -979,6 +979,9 @@ class_item /* IEEE1800-2005: A.1.8 */
 
   | parameter_declaration
 
+    /* Empty class item */
+  | ';'
+
   | error ';'
       { yyerror(@2, "error: invalid class item.");
 	yyerrok;