Spelling fixes

only comments and documentation

examples/pal_reg.v

@@ -26,7 +26,7 @@
  *   iverilog -tpal -ppart=generic-22v10-plcc -opal_reg.jed pal_reg.v
  *
  * The output file name (passed through the -o<file> switch) can be
- * any file you desire. If the compilation and fittin all succeed, the
+ * any file you desire. If the compilation and fitting all succeed, the
  * output file will be a JEDEC file that you can take to your favorite
  * PROM programmer to program the part.
  *
@@ -45,7 +45,7 @@
  *
  * The output drivers are controlled by a single active low output
  * enable. I used bufif0 devices in this example, but the exact same
- * thing can be achived with a continuous assignment like so:
+ * thing can be achieved with a continuous assignment like so:
  *
  *   assign out = oe? 8'hzz : Q;
  *
@@ -76,7 +76,7 @@ endmodule
  * a PLCC package.
  *
  * Note that this module has no logic in it. It is a convention I use
- * that I put all the functionality in a seperate module (seen above)
+ * that I put all the functionality in a separate module (seen above)
  * and isolate the Icarus Verilog specific $attribute madness into a
  * top-level module. The advantage of this style is that the entire
  * module can be `ifdef'ed out when doing simulation and you don't

examples/show_vcd.vl

@@ -63,7 +63,7 @@
   *
   *  The $dumpvars task tells the simulation what variables to write to
   *  the VCD output. The first parameter is how far to descend while
-  *  scanning a scope, and the remaining paramters are signals or scope
+  *  scanning a scope, and the remaining parameters are signals or scope
   *  names to include in the dump. If a scope name is given, all the
   *  signals within the scope are dumped. If a wire or register name is
   *  given, that signal is included.

examples/sqrt-virtex.v

@@ -20,7 +20,7 @@
  */
 
 /*
- * This module is a synthesizeable square-root function. It is also a
+ * This module is a synthesizable square-root function. It is also a
  * detailed example of how to target Xilinx Virtex parts using
  * Icarus Verilog. In fact, for no particular reason other than to
  * be excessively specific, I will step through the process of
@@ -30,7 +30,7 @@
  * In addition to Icarus Verilog, you will need implementation
  * software from Xilinx. As of this writing, this example was tested
  * with Foundation 4.2i, but it should work the same with ISE and
- * Webpack software.
+ * WebPACK software.
  *
  * This example source contains all the Verilog needed to do
  * everything described below. We use conditional compilation to
@@ -55,7 +55,7 @@
  * "PASSED" and finishes the simulation.
  *
  * When you take a close look at the "main" module below, you will see
- * that it uses Verilog constructs that are not synthesizeable. This
+ * that it uses Verilog constructs that are not synthesizable. This
  * is fine, as we will never try to synthesize it.
  *
  * LIBRARY PARTS
@@ -78,7 +78,7 @@
  * Without any preprocessor directives, the only module is the sqrt32
  * module, so sqrt32 is compiled as the root. The ports of the module
  * are automatically made into ports of the sqrt32.edf netlist, and
- * the contents of the sqrt32 module are connected approprately.
+ * the contents of the sqrt32 module are connected appropriately.
  *
  * COMPLETE CHIP DESIGNS
  *