diff --git a/BUGS.txt b/BUGS.txt index 9b066e7b8..f41589392 100644 --- a/BUGS.txt +++ b/BUGS.txt @@ -72,7 +72,7 @@ reporting problems with. However, if you clearly explain what is right and wrong about the generated netlist, I will probably be able to fix the problem. It may take a few iterations. -In this case, if possible include not only the sample verilog program, +In this case, if possible include not only the sample Verilog program, but the generated netlist file(s) and a clear indication of what went wrong. If it is not clear to me, I will ask for clarification. diff --git a/examples/pal_reg.v b/examples/pal_reg.v index a3731a5f8..f959a6e1b 100644 --- a/examples/pal_reg.v +++ b/examples/pal_reg.v @@ -26,7 +26,7 @@ * iverilog -tpal -ppart=generic-22v10-plcc -opal_reg.jed pal_reg.v * * The output file name (passed through the -o switch) can be - * any file you desire. If the compilation and fittin all succeed, the + * any file you desire. If the compilation and fitting all succeed, the * output file will be a JEDEC file that you can take to your favorite * PROM programmer to program the part. * @@ -45,7 +45,7 @@ * * The output drivers are controlled by a single active low output * enable. I used bufif0 devices in this example, but the exact same - * thing can be achived with a continuous assignment like so: + * thing can be achieved with a continuous assignment like so: * * assign out = oe? 8'hzz : Q; * @@ -76,7 +76,7 @@ endmodule * a PLCC package. * * Note that this module has no logic in it. It is a convention I use - * that I put all the functionality in a seperate module (seen above) + * that I put all the functionality in a separate module (seen above) * and isolate the Icarus Verilog specific $attribute madness into a * top-level module. The advantage of this style is that the entire * module can be `ifdef'ed out when doing simulation and you don't diff --git a/examples/show_vcd.vl b/examples/show_vcd.vl index a3325eeda..d0a6d7e69 100644 --- a/examples/show_vcd.vl +++ b/examples/show_vcd.vl @@ -63,7 +63,7 @@ * * The $dumpvars task tells the simulation what variables to write to * the VCD output. The first parameter is how far to descend while - * scanning a scope, and the remaining paramters are signals or scope + * scanning a scope, and the remaining parameters are signals or scope * names to include in the dump. If a scope name is given, all the * signals within the scope are dumped. If a wire or register name is * given, that signal is included. diff --git a/examples/sqrt-virtex.v b/examples/sqrt-virtex.v index c0b266d69..410e6e744 100644 --- a/examples/sqrt-virtex.v +++ b/examples/sqrt-virtex.v @@ -20,7 +20,7 @@ */ /* - * This module is a synthesizeable square-root function. It is also a + * This module is a synthesizable square-root function. It is also a * detailed example of how to target Xilinx Virtex parts using * Icarus Verilog. In fact, for no particular reason other than to * be excessively specific, I will step through the process of @@ -30,7 +30,7 @@ * In addition to Icarus Verilog, you will need implementation * software from Xilinx. As of this writing, this example was tested * with Foundation 4.2i, but it should work the same with ISE and - * Webpack software. + * WebPACK software. * * This example source contains all the Verilog needed to do * everything described below. We use conditional compilation to @@ -55,7 +55,7 @@ * "PASSED" and finishes the simulation. * * When you take a close look at the "main" module below, you will see - * that it uses Verilog constructs that are not synthesizeable. This + * that it uses Verilog constructs that are not synthesizable. This * is fine, as we will never try to synthesize it. * * LIBRARY PARTS @@ -78,7 +78,7 @@ * Without any preprocessor directives, the only module is the sqrt32 * module, so sqrt32 is compiled as the root. The ports of the module * are automatically made into ports of the sqrt32.edf netlist, and - * the contents of the sqrt32 module are connected approprately. + * the contents of the sqrt32 module are connected appropriately. * * COMPLETE CHIP DESIGNS * diff --git a/mingw.txt b/mingw.txt index fa15b5477..19e861d7d 100644 --- a/mingw.txt +++ b/mingw.txt @@ -91,7 +91,7 @@ commands below. The obvious step 2, then, is install the mingw compilers. These can be found at the web page . The Mingw-5.x.x package is a convenient remote installer. Download this program and run -it. The installer will ask wich components you want to install. You +it. The installer will ask which components you want to install. You need only the base C compiler and the C++ compiler. (You may install other languages if you wish.) @@ -150,7 +150,7 @@ You will need these gnuwin32 packages to compile Icarus Verilog: I suggest creating a common directory for holding all your gnuwin32 packages. I use C:\gnuwin32. The download page at the gnuwin32 site has a "setup" link for each of these packages. Click the setup to -download the installer for each of the desired programes, then execute +download the installer for each of the desired programs, then execute the downloaded .exe files to invoke the installer. Install into the c:\gunwin32 directory. diff --git a/net_nex_output.cc b/net_nex_output.cc index 03a38673f..e2d025784 100644 --- a/net_nex_output.cc +++ b/net_nex_output.cc @@ -105,7 +105,7 @@ void NetPDelay::nex_output(NexusSet&out) /* * For the purposes of synthesis, system task calls have no output at - * all. This is OK because most system tasks are not synthesizeable in + * all. This is OK because most system tasks are not synthesizable in * the first place. */ void NetSTask::nex_output(NexusSet&out) diff --git a/verinum.cc b/verinum.cc index 74e5eec0c..de56b3e58 100644 --- a/verinum.cc +++ b/verinum.cc @@ -290,7 +290,7 @@ uint64_t verinum::as_ulong64() const * * If the value is undefined, return 0. * - * This function presumes that the native format is 2s compliment + * This function presumes that the native format is 2s complement * (pretty safe these days) and masks/sets bits accordingly. If the * value is too large for the native form, it truncates the high bits. */ diff --git a/vvp/README.txt b/vvp/README.txt index a9efba5b4..bf24c98af 100644 --- a/vvp/README.txt +++ b/vvp/README.txt @@ -140,8 +140,8 @@ The value, then, is appropriate for the data type. For example: P_123 .param/str "hello", "Hello, World."; The boolean and logic values can also be signed or not. If signed, the -value is preceeded by a '+' character. (Note that the value is 2s -compliment, so the '+' says only that it is signed, not positive.) +value is preceded by a '+' character. (Note that the value is 2s +complement, so the '+' says only that it is signed, not positive.) FUNCTOR STATEMENTS: @@ -333,8 +333,8 @@ that arrive through them, while .net nodes reduce strength values to 4-value logic. The .net8 nodes should only be used when strength information really is possible. -The