From 37f7308f80f472c065231d8fca7175862f30f02f Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 11 Jun 2023 07:54:56 -0700 Subject: [PATCH] Add regression test for omitting trailing ports in ordered list connection Check that it is possible to omit trailing ports in a module ordered list connection list. Also check that an error is generated if too many ports are specified in a ordered list connection. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/module_ordered_list1.v | 35 ++++++++++++++++++++++ ivtest/ivltests/module_ordered_list2.v | 24 +++++++++++++++ ivtest/regress-vvp.list | 2 ++ ivtest/vvp_tests/module_ordered_list1.json | 5 ++++ ivtest/vvp_tests/module_ordered_list2.json | 4 +++ 5 files changed, 70 insertions(+) create mode 100644 ivtest/ivltests/module_ordered_list1.v create mode 100644 ivtest/ivltests/module_ordered_list2.v create mode 100644 ivtest/vvp_tests/module_ordered_list1.json create mode 100644 ivtest/vvp_tests/module_ordered_list2.json diff --git a/ivtest/ivltests/module_ordered_list1.v b/ivtest/ivltests/module_ordered_list1.v new file mode 100644 index 000000000..63285acfc --- /dev/null +++ b/ivtest/ivltests/module_ordered_list1.v @@ -0,0 +1,35 @@ +// Check that it is possible to omit trailing module ports in a ordered list +// connection if the trailing port has a default value. + +module M ( + output logic a, + input logic b, + input logic c = 1'b0, + input logic d = 1'b1 +); + assign a = b ^ c ^ d; +endmodule + +module test; + + logic a, b, c; + logic x, y; + + assign b = 1'b0; + assign c = 1'b1; + + assign y = 1'b1; + + M i_M1 (a, b, c); + M i_M2 (x, y); + + initial begin + #1 + if (a !== 1'b0 || x !== 1'b0) begin + $display("FAILED"); + end else begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/ivltests/module_ordered_list2.v b/ivtest/ivltests/module_ordered_list2.v new file mode 100644 index 000000000..16b367d40 --- /dev/null +++ b/ivtest/ivltests/module_ordered_list2.v @@ -0,0 +1,24 @@ +// Check that an error is reported when specifying too many ports in a ordered +// list connection. + +module M ( + output a, + input b +); + assign a = b; +endmodule + +module test; + + wire a, b, c; + + assign b = 1'b0; + assign c = 1'b1; + + M i_M (a, b, c); // Error, too many ports. + + initial begin + $display("FAILED"); + end + +endmodule diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index 681dd1a81..1c3ddd4f3 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -26,6 +26,8 @@ dumpfile vvp_tests/dumpfile.json final3 vvp_tests/final3.json macro_str_esc vvp_tests/macro_str_esc.json memsynth1 vvp_tests/memsynth1.json +module_ordered_list1 vvp_tests/module_ordered_list1.json +module_ordered_list2 vvp_tests/module_ordered_list2.json module_port_array1 vvp_tests/module_port_array1.json param-width vvp_tests/param-width.json param-width-vlog95 vvp_tests/param-width-vlog95.json diff --git a/ivtest/vvp_tests/module_ordered_list1.json b/ivtest/vvp_tests/module_ordered_list1.json new file mode 100644 index 000000000..d2d5c338d --- /dev/null +++ b/ivtest/vvp_tests/module_ordered_list1.json @@ -0,0 +1,5 @@ +{ + "type" : "normal", + "source" : "module_ordered_list1.v", + "iverilog-args" : [ "-g2005-sv" ] +} diff --git a/ivtest/vvp_tests/module_ordered_list2.json b/ivtest/vvp_tests/module_ordered_list2.json new file mode 100644 index 000000000..fe4a27a0e --- /dev/null +++ b/ivtest/vvp_tests/module_ordered_list2.json @@ -0,0 +1,4 @@ +{ + "type" : "CE", + "source" : "module_ordered_list2.v" +}