From 34bb98676a50727024ab0026d801a8b0895ab0d1 Mon Sep 17 00:00:00 2001 From: Martin Whitaker Date: Sat, 7 Sep 2019 14:35:19 +0100 Subject: [PATCH] Fix assertion failure on illegal SV cast. Bug reported on iverilog-devel on 2018-02027. --- elab_expr.cc | 6 ++++-- netmisc.cc | 15 +++++++++++++++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/elab_expr.cc b/elab_expr.cc index b2845fbd4..cb9a88158 100644 --- a/elab_expr.cc +++ b/elab_expr.cc @@ -1107,12 +1107,14 @@ unsigned PECallFunction::test_width_sfunc_(Design*des, NetScope*scope, bool rc = eval_as_long(value, nexpr); ivl_assert(*this, rc && value>=0); - // The argument type/width is self-determined and doesn't - // affect the result type/width. + // The argument width is self-determined and doesn't + // affect the result width. width_mode_t arg_mode = SIZED; parms_[0]->test_width(des, scope, arg_mode); + expr_type_ = pexpr->expr_type(); expr_width_ = value; + min_width_ = value; signed_flag_= false; return expr_width_; } diff --git a/netmisc.cc b/netmisc.cc index 59da76061..427fd56e2 100644 --- a/netmisc.cc +++ b/netmisc.cc @@ -925,6 +925,21 @@ static NetExpr* do_elab_and_eval(Design*des, NetScope*scope, PExpr*pe, if (tmp == 0) return 0; if ((cast_type != IVL_VT_NO_TYPE) && (cast_type != tmp->expr_type())) { + if (cast_type != pe->expr_type()) { + switch (pe->expr_type()) { + case IVL_VT_BOOL: + case IVL_VT_LOGIC: + case IVL_VT_REAL: + break; + default: + cerr << tmp->get_fileline() << ": error: " + "this expression cannot be implicitly " + "cast to the target type." << endl; + des->errors += 1; + delete tmp; + return 0; + } + } switch (cast_type) { case IVL_VT_REAL: tmp = cast_to_real(tmp);