Elaborate input port default value expressions in the correct scope

elaborate.cc

@@ -1482,10 +1482,17 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 	      // Count the internal vector bits of the port.
 	    unsigned prts_vector_width = 0;
 
+
+	      // The input expression is normally elaborated in the calling
+	      // scope, except when the defult expression is used which is
+	      // elaborated in the instance scope.
+	    vector<NetScope*> elab_scope_inst(instance.size());
 	    for (unsigned inst = 0 ;  inst < instance.size() ;  inst += 1) {
+		  elab_scope_inst[inst] = scope;
 		    // Scan the instances from MSB to LSB. The port
 		    // will be assembled in that order as well.
 		  NetScope*inst_scope = instance[instance.size()-inst-1];
+		  if (using_default) elab_scope_inst[inst] = inst_scope;
 
 		  unsigned int prt_vector_width = 0;
 		  PortType::Enum ptype = PortType::PIMPLICIT;
@@ -1583,12 +1590,36 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 			if (literal->value().is_single())
 			      context_width = prts_vector_width;
 		  }
-		  NetExpr*tmp_expr = elab_and_eval(des, scope, pins[idx], context_width, using_default);
+		    // FIXME: The default value is getting the wrong value for
+		    //        an array instance since only one scope is used
+		    //        and the value can be different for each scope.
+		    //        Need to rework the code to support this.
+		  NetScope* elab_scope = scope;
+		  if (using_default) {
+//if (instance.size() > 1) {
+//      for (unsigned inst = 0 ;  inst < instance.size() ;  inst += 1) {
+//	    cerr << get_fileline() << ": FIXME: Instance " << inst
+//	         << " has scope: " << elab_scope_inst[inst]->fullname() << endl;
+//      }
+//}
+			if (instance.size() > 1) {
+			      cerr << get_fileline() << ": sorry: An input port "
+			           << "default value is not currently supported "
+			           << "for a module instance array." << endl;
+			      des->errors += 1;
+			      continue;
+			}
+			elab_scope = elab_scope_inst[0];
+		  }
+		  NetExpr*tmp_expr = elab_and_eval(des, elab_scope, pins[idx], context_width, using_default);
 		  if (tmp_expr == 0) {
 			cerr << pins[idx]->get_fileline()
-			     << ": error: Failed to elaborate port "
+			     << ": error: Failed to elaborate input port '"
-			     << (using_default ? "default value." : "expression.")
+			     << port_name << "' "
-			     << endl;
+			     << (using_default ? "default value" : "expression")
+			     << " (" << *pins[idx] << ") in instance "
+			     << scope->fullname() << "." << get_name()
+			     << " of module: " << rmod->mod_name() << "." << endl;
 			des->errors += 1;
 			continue;
 		  }

ivtest/gold/pr1833024.gold

@@ -31,13 +31,13 @@
 ./ivltests/pr1833024.v:32: error: can not select part of scalar: wsuptr
 ./ivltests/pr1833024.v:33: error: can not select part of scalar: wsdotr
 ./ivltests/pr1833024.v:35: error: can not select part of scalar: wsbstr
-./ivltests/pr1833024.v:35: error: Failed to elaborate port expression.
+./ivltests/pr1833024.v:35: error: Failed to elaborate input port 'arg1' expression (wsbstr['sd0]) in instance top.s1 of module: submod1.
 ./ivltests/pr1833024.v:35: error: can not select part of scalar: wspstr
-./ivltests/pr1833024.v:35: error: Failed to elaborate port expression.
+./ivltests/pr1833024.v:35: error: Failed to elaborate input port 'arg2' expression (wspstr['sd0:'sd0]) in instance top.s1 of module: submod1.
 ./ivltests/pr1833024.v:35: error: can not select part of scalar: wsuptr
-./ivltests/pr1833024.v:35: error: Failed to elaborate port expression.
+./ivltests/pr1833024.v:35: error: Failed to elaborate input port 'arg3' expression (wsuptr['sd0+:'sd1]) in instance top.s1 of module: submod1.
 ./ivltests/pr1833024.v:35: error: can not select part of scalar: wsdotr
-./ivltests/pr1833024.v:35: error: Failed to elaborate port expression.
+./ivltests/pr1833024.v:35: error: Failed to elaborate input port 'arg4' expression (wsdotr['sd0-:'sd1]) in instance top.s1 of module: submod1.
 ./ivltests/pr1833024.v:36: error: can not select part of scalar: wsbstr
 ./ivltests/pr1833024.v:36: error: Output port expression must support continuous assignment.
 ./ivltests/pr1833024.v:36:      : Port 1 (arg1) of submod2 is connected to wsbstr['sd0]

ivtest/gold/sv_default_port_value3-iverilog-stderr.gold

@@ -1,3 +1,3 @@
 ivltests/sv_default_port_value3.v:3: error: A reference to a net or variable (`v') is not allowed in a constant expression.
-ivltests/sv_default_port_value3.v:3: error: Failed to elaborate port default value.
+ivltests/sv_default_port_value3.v:3: error: Failed to elaborate input port 'i' default value (v) in instance tb.dut of module: dut.
 2 error(s) during elaboration.

ivtest/ivltests/br_gh1230.v

@@ -0,0 +1,25 @@
+module Foo #(parameter logic F = 1'b1) (input logic i = F);
+  initial begin
+    #1;
+    $display("%m has an input value of %b.", i);
+    if (i !== F) begin
+      $display("FAILED: %m.i = %b ,expected %b!", i, F);
+      Test.passed = 1'b0;
+    end
+  end
+endmodule
+
+module Test;
+  reg passed;
+  initial passed = 1'b1;
+
+// FIXME: A default value is not currently supported for
+//        a module instance array.
+//  defparam e[0].F = 1'b0;
+//  Foo e[1:0]();
+  defparam g.F = 1'b0;
+  Foo f(), g();
+  Foo #(.F(1'bz)) h();
+
+  final if (passed) $display("PASSED");
+endmodule

ivtest/regress-sv.list

@@ -232,6 +232,7 @@ br_gh1222		CE,-g2009		ivltests gold=br_gh1222.gold
 br_gh1223a		normal,-g2009		ivltests
 br_gh1223b		normal,-g2009		ivltests
 br_gh1223c		normal,-g2009		ivltests
+br_gh1230		normal,-g2009		ivltests
 br_ml20171017		normal,-g2009		ivltests
 br_ml20180227		CE,-g2009		ivltests
 br_ml20180309a		normal,-g2009		ivltests

ivtest/regress-vlog95.list

@@ -261,6 +261,7 @@ concat4			EF			ivltests
 
 # SystemVerilog final blocks are not supported.
 br_gh443		CE,-g2009		ivltests
+br_gh1230		CE,-g2009		ivltests
 final			CE,-g2009		ivltests
 final2			CE,-g2009		ivltests
 program_hello		CE,-g2009		ivltests