diff --git a/tgt-vhdl/expr.cc b/tgt-vhdl/expr.cc
index 3501bc188..ead20f2bf 100644
--- a/tgt-vhdl/expr.cc
+++ b/tgt-vhdl/expr.cc
@@ -33,6 +33,16 @@ static vhdl_expr *translate_string(ivl_expr_t e)
    return new vhdl_const_string(str);
 }
 
+/*
+ * A reference to a signal in an expression. It's assumed that the
+ * signal has already been defined elsewhere.
+ */
+static vhdl_expr *translate_signal(ivl_expr_t e)
+{
+   ivl_signal_t sig = ivl_expr_signal(e);
+   return new vhdl_var_ref(ivl_signal_basename(sig));
+}
+
 /*
  * Generate a VHDL expression from a Verilog expression.
  */
@@ -43,6 +53,8 @@ vhdl_expr *translate_expr(ivl_expr_t e)
    switch (type) {
    case IVL_EX_STRING:
       return translate_string(e);
+   case IVL_EX_SIGNAL:
+      return translate_signal(e);
    default:
       error("No VHDL translation for expression at %s:%d (type = %d)",
             ivl_expr_file(e), ivl_expr_lineno(e), type);
diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc
index 44b8ebc4a..e5e70d64b 100644
--- a/tgt-vhdl/stmt.cc
+++ b/tgt-vhdl/stmt.cc
@@ -178,23 +178,12 @@ static int draw_wait(vhdl_process *proc, ivl_statement_t stmt)
             ivl_signal_t sig;
             if ((sig = ivl_nexus_ptr_sig(nexus_ptr))) {
                const char *signame = ivl_signal_basename(sig);
-               std::cout << "signal " << signame << std::endl;
-
-               if (!proc->get_parent()->have_declared(signame)) {
-                  // First time this signal has been encountered
-                  vhdl_scalar_type *std_logic =
-                     new vhdl_scalar_type("std_logic");
-                  vhdl_signal_decl *sig_decl =
-                     new vhdl_signal_decl(signame, std_logic);
-                  
-                  proc->get_parent()->add_decl(sig_decl);
-               }
-                  
+               std::cout << "signal " << signame << std::endl;               
                proc->add_sensitivity(signame);
             }
             else if ((log = ivl_nexus_ptr_log(nexus_ptr))) {
-               error("Nexus points to net logic");
-               return 1;
+               std::cout << "net logic " << ivl_logic_basename(log) << " ";
+               std::cout << "type = " << ivl_logic_type(log) << std::endl;
             }
             else {
                error("Nexus points to unknown");