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Fix GitHub issue #352 - typo in README.txt (%time -> $time).

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Martin Whitaker 2020-08-05 11:33:34 +01:00
parent a0ef23605a
commit 2f317065aa
1 changed files with 1 additions and 1 deletions
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README.txt
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@ -436,7 +436,7 @@ more details.
Standard Verilog does not allow width fields in the %t formats Standard Verilog does not allow width fields in the %t formats
of display strings. For example, this is illegal: of display strings. For example, this is illegal:
$display("Time is %0t", %time); $display("Time is %0t", $time);
Standard Verilog instead relies on the $timeformat to Standard Verilog instead relies on the $timeformat to
completely specify the format. completely specify the format.