From 2f317065aa235a7e8124551851650d737b3a3290 Mon Sep 17 00:00:00 2001
From: Martin Whitaker <icarus@martin-whitaker.me.uk>
Date: Wed, 5 Aug 2020 11:33:34 +0100
Subject: [PATCH] Fix GitHub issue #352 - typo in README.txt (%time -> $time).

---
 README.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.txt b/README.txt
index 87688961c..26533ebcf 100644
--- a/README.txt
+++ b/README.txt
@@ -436,7 +436,7 @@ more details.
 	Standard Verilog does not allow width fields in the %t formats
 	of display strings. For example, this is illegal:
 
-		$display("Time is %0t", %time);
+		$display("Time is %0t", $time);
 
 	Standard Verilog instead relies on the $timeformat to
 	completely specify the format.