diff --git a/ivtest/ivltests/pr1002.v b/ivtest/ivltests/pr1002.v
index ce11d5a97..ff8ff7b72 100644
--- a/ivtest/ivltests/pr1002.v
+++ b/ivtest/ivltests/pr1002.v
@@ -8,29 +8,11 @@ assign dataout = datain >>> 2;
 
 reg test_failed;
 
-initial
-  begin
-     test_failed = 0;
-     #1 datain = 14'h0FFF;
-     #1 datain = 14'h0000;
-     #1 datain = 14'h1FFF;
-     #1 datain = 14'h1000;
-     #1 datain = 14'h2FFF;
-     #1 datain = 14'h2000;
-     #1 datain = 14'h3FFF;
-     #1 datain = 14'h3000;
-     #2;
-     if (test_failed)
-       $display("TEST FAILED :-(");
-     else
-       $display("TEST PASSED :-)");
-  end
-
 wire signed [15:0] expected_dataout;
 
 assign expected_dataout = ($signed({datain[13:2], 2'b0}) / 4) ;
 
-always @(dataout)
+task check_data;
   if (expected_dataout != dataout)
     begin
        $display("datain = %d dataout = %h expected = %h ... CHECK FAILED", datain, dataout, expected_dataout);
@@ -38,5 +20,32 @@ always @(dataout)
     end
   else
     $display("datain = %d dataout = %d expected = %d ... CHECK PASSED", datain, dataout, expected_dataout);
+endtask
+
+initial
+  begin
+     test_failed = 0;
+     #1 datain = 14'h0FFF;
+     #0 check_data; // #0 delay to allow the wire to resolve
+     #1 datain = 14'h0000;
+     #0 check_data;
+     #1 datain = 14'h1FFF;
+     #0 check_data;
+     #1 datain = 14'h1000;
+     #0 check_data;
+     #1 datain = 14'h2FFF;
+     #0 check_data;
+     #1 datain = 14'h2000;
+     #0 check_data;
+     #1 datain = 14'h3FFF;
+     #0 check_data;
+     #1 datain = 14'h3000;
+     #0 check_data;
+     #2;
+     if (test_failed)
+       $display("TEST FAILED :-(");
+     else
+       $display("TEST PASSED :-)");
+  end
 
 endmodule // top