diff --git a/elab_sig.cc b/elab_sig.cc
index 9f762c5ad..6f778f669 100644
--- a/elab_sig.cc
+++ b/elab_sig.cc
@@ -144,10 +144,12 @@ static void sig_check_port_type(Design*des, NetScope*scope,
 	    return;
 
 	/* If the signal is an input and is also declared as a
-	   reg, then report an error. */
+	   reg, then report an error. In SystemVerilog a input
+	   is allowed to be a register. It will get converted
+	   to a unresolved wire when the port is connected. */
 
       if (sig->port_type() == NetNet::PINPUT &&
-	  sig->type() == NetNet::REG) {
+	  sig->type() == NetNet::REG && !gn_var_can_be_uwire()) {
 	    cerr << wire->get_fileline() << ": error: Port `"
 		 << wire->basename() << "` of module `"
 		 << scope->module_name()
diff --git a/elaborate.cc b/elaborate.cc
index 6357d6f14..6a38d8b16 100644
--- a/elaborate.cc
+++ b/elaborate.cc
@@ -1533,6 +1533,13 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
 		  delete tmp_expr;
 		  if (!sig->get_lineno()) sig->set_line(*this);
 
+		  if (ptype == NetNet::PINPUT && gn_var_can_be_uwire()) {
+			for (unsigned int i = 0; i < prts.size(); i++) {
+			      if (prts[i]->type() == NetNet::REG)
+				    prts[i]->type(NetNet::UNRESOLVED_WIRE);
+			}
+		  }
+
 		  if (need_bufz_for_input_port(prts)) {
 			NetBUFZ*tmp = new NetBUFZ(scope, scope->local_symbol(),
 						  sig->vector_width(), true);