From 7bf4b64c0ad3b1e12281a39a4b78b827dca2c6f8 Mon Sep 17 00:00:00 2001 From: Cary R Date: Wed, 29 Aug 2007 17:29:56 -0700 Subject: [PATCH 1/2] Check that logic gates are not given null ports. Logic gates do not handle null ports so check for this and issue an error message when it happens. --- elaborate.cc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/elaborate.cc b/elaborate.cc index e3b3463c0..c61d033bc 100644 --- a/elaborate.cc +++ b/elaborate.cc @@ -379,6 +379,12 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const only. We do it early so that we can see if we can make a wide gate instead of an array of gates. */ + if (pin(0) == 0) { + cerr << get_line() << ": error: Logic gate port " + "expressions are not optional." << endl; + des->errors += 1; + return; + } NetNet*lval_sig = pin(0)->elaborate_lnet(des, scope, true); assert(lval_sig); @@ -536,6 +542,12 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const for (unsigned idx = 0 ; idx < pin_count() ; idx += 1) { const PExpr*ex = pin(idx); + if (ex == 0) { + cerr << get_line() << ": error: Logic gate port " + "expressions are not optional." << endl; + des->errors += 1; + return; + } NetNet*sig = (idx == 0) ? lval_sig : ex->elaborate_net(des, scope, 0, 0, 0, 0); From b55e3c11dca4cf890df42cfc37f472b010dd72d5 Mon Sep 17 00:00:00 2001 From: Cary R Date: Thu, 30 Aug 2007 15:39:46 -0700 Subject: [PATCH 2/2] mingw needs fseeko/ftello redefinitions in lxt_write.h These redefinitions were in lxt2_write.h, but missing in lxt_write.h. This patch adds them to lxt_write.h. --- vpi/lxt_write.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/vpi/lxt_write.h b/vpi/lxt_write.h index f017a4d98..6a2ea50b2 100644 --- a/vpi/lxt_write.h +++ b/vpi/lxt_write.h @@ -32,6 +32,11 @@ #include #include +#if defined _MSC_VER || defined __MINGW32__ +#define fseeko fseek +#define ftello ftell +#endif + typedef struct dslxt_tree_node dslxt_Tree; struct dslxt_tree_node {