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Fix check for SV continuous assign to variable. 

SystemVerilog allows a variable to be used as a variable OR
as an unresolved wire. The detection of this case was checking
the references to the affected value, instead of the l-value
references.
(cherry picked from commit cceeaa30f27260cd444015cb39b04353cb858768)
This commit is contained in:
Stephen Williams 2012-04-15 18:04:09 -07:00
parent 75b12151a4
commit 2013addd22
1 changed files with 1 additions and 1 deletions
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2
elab_net.cc
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@ -443,7 +443,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
wire. */ wire. */
if (gn_var_can_be_uwire() if (gn_var_can_be_uwire()
&& (sig->type() == NetNet::REG) && (sig->type() == NetNet::REG)
&& (sig->peek_eref() == 0) ) { && (sig->peek_lref() == 0) ) {
sig->type(NetNet::UNRESOLVED_WIRE); sig->type(NetNet::UNRESOLVED_WIRE);
} }