From 2013addd22a3b9cc05bb30a3367830671e1aadf9 Mon Sep 17 00:00:00 2001
From: Stephen Williams <steve@icarus.com>
Date: Sun, 15 Apr 2012 18:04:09 -0700
Subject: [PATCH] Fix check for SV continuous assign to variable.

SystemVerilog allows a variable to be used as a variable OR
as an unresolved wire. The detection of this case was checking
the references to the affected value, instead of the l-value
references.
(cherry picked from commit cceeaa30f27260cd444015cb39b04353cb858768)
---
 elab_net.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/elab_net.cc b/elab_net.cc
index 163e543cc..db70c4069 100644
--- a/elab_net.cc
+++ b/elab_net.cc
@@ -443,7 +443,7 @@ NetNet* PEIdent::elaborate_lnet_common_(Design*des, NetScope*scope,
 	   wire. */
       if (gn_var_can_be_uwire()
 	  && (sig->type() == NetNet::REG)
-	  && (sig->peek_eref() == 0) ) {
+	  && (sig->peek_lref() == 0) ) {
 	    sig->type(NetNet::UNRESOLVED_WIRE);
       }