From 1de3fb162563a46dba0ca95b754ba98e692e6929 Mon Sep 17 00:00:00 2001 From: Maciej Suminski Date: Mon, 2 Mar 2015 16:35:51 +0100 Subject: [PATCH] vhdlpp: "resize" function. --- vhdlpp/expression_emit.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/vhdlpp/expression_emit.cc b/vhdlpp/expression_emit.cc index 7dee9ee47..bb88ddfe5 100644 --- a/vhdlpp/expression_emit.cc +++ b/vhdlpp/expression_emit.cc @@ -560,12 +560,13 @@ int ExpFunc::emit(ostream&out, Entity*ent, ScopeBase*scope) { int errors = 0; - // SystemVerilog takes care of signs, depending on the lvalue - if (name_ == "to_integer" && argv_.size()==1) { + // SystemVerilog takes care of sign & width, depending on the lvalue type + if ((name_ == "to_integer" && argv_.size() == 1) || + (name_ == "resize" && argv_.size() == 2)) { errors += argv_[0]->emit(out, ent, scope); } - else if (name_ == "unsigned" && argv_.size()==1) { + else if (name_ == "unsigned" && argv_.size() == 1) { // Handle the special case that this is a cast to // unsigned. This function is brought in as part of the // std numeric library, but we interpret it as the same