List parameters/values in VHDL entity comment

For example:

  -- Generated from Verilog module child (vhdl_tests/generics.v:30)
  --   MY_VALUE = 3
  entity child is

To make it clear which values were used for this entity.

Conflicts:

	tgt-vhdl/scope.cc

tgt-vhdl/scope.cc

@@ -926,6 +926,26 @@ static void create_skeleton_entity_for(ivl_scope_t scope, int depth)
       << " (" << ivl_scope_def_file(scope) << ":"
       << ivl_scope_def_lineno(scope) << ")";
 
+   unsigned nparams = ivl_scope_params(scope);
+   for (unsigned i = 0; i < nparams; i++) {
+      ivl_parameter_t param = ivl_scope_param(scope, i);
+      ss << "\n  " << ivl_parameter_basename(param) << " = ";
+
+      ivl_expr_t value = ivl_parameter_expr(param);
+      switch (ivl_expr_type(value)) {
+         case IVL_EX_STRING:
+            ss << "\"" << ivl_expr_string(value) << "\"";
+            break;
+
+         case IVL_EX_NUMBER:
+            ss << ivl_expr_value(value);
+            break;
+
+      default:
+         assert(false);
+      }
+   }
+   
    arch->set_comment(ss.str());
    ent->set_comment(ss.str());
 

tgt-vhdl/vhdl_element.cc

@@ -81,10 +81,21 @@ void vhdl_element::emit_comment(std::ostream &of, int level,
 {
    if (comment_.size() > 0) {
       if (end_of_line)
-         of << "  ";
+         of << "  -- " << comment_;
-      of << "-- " << comment_;
+      else {
-      if (!end_of_line)
+         // Comment may contain embedded newlines
+         of << "-- ";
+         for (string::const_iterator it = comment_.begin();
+              it != comment_.end(); ++it) {
+            if (*it == '\n') {
+               newline(of, level);
+               of << "-- ";
+            }
+            else
+               of << *it;
+         }
          newline(of, level);
+      }
    }
 }