From 172d7eb0a3665f89b91d601b5912c33acedc81e5 Mon Sep 17 00:00:00 2001
From: Cary R <cygcary@yahoo.com>
Date: Tue, 13 Nov 2018 21:57:08 -0800
Subject: [PATCH] Fix space issues in a couple files

---
 README.txt       | 4 ++--
 tgt-vhdl/stmt.cc | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/README.txt b/README.txt
index 3ba1503db..96a48cf4a 100644
--- a/README.txt
+++ b/README.txt
@@ -77,12 +77,12 @@ the configure scripts.
 Unpack the tar-ball and cd into the verilog-######### directory
 (presumably that is how you got to this README) and compile the source
 with the commands:
-	
+
   ./configure
   make
 
 If you are building from git, you have to run the command below before
-compile the source. This will generate the "configure" file, which is 
+compile the source. This will generate the "configure" file, which is
 automatically done when building from tarball.
 
   sh autoconf.sh
diff --git a/tgt-vhdl/stmt.cc b/tgt-vhdl/stmt.cc
index 51ac8bb20..6d9c7f437 100644
--- a/tgt-vhdl/stmt.cc
+++ b/tgt-vhdl/stmt.cc
@@ -1250,7 +1250,7 @@ static void process_number(vhdl_binop_expr *all, vhdl_var_ref *test,
       switch (bits[i]) {
       case 'x':
          if (is_casez) break;
-         // fallthrough 
+         // fallthrough
       case '?':
       case 'z':
          continue;  // Ignore these.