From 167a6bbcdb6293f7c8d4efbbc2e1b0c9b3c8348b Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sat, 20 Jun 2026 15:30:10 -0700 Subject: [PATCH] Add regression test for case muxes with array word inputs Check that synthesized case statement muxes can use array words as inputs. This used to generate invalid VVP because .array/port statements were emitted in the middle of .functor statements. Signed-off-by: Lars-Peter Clausen --- ivtest/ivltests/case_mux_array_word.v | 52 +++++++++++++++++++++++ ivtest/regress-vvp.list | 1 + ivtest/vvp_tests/case_mux_array_word.json | 5 +++ 3 files changed, 58 insertions(+) create mode 100644 ivtest/ivltests/case_mux_array_word.v create mode 100644 ivtest/vvp_tests/case_mux_array_word.json diff --git a/ivtest/ivltests/case_mux_array_word.v b/ivtest/ivltests/case_mux_array_word.v new file mode 100644 index 000000000..800798482 --- /dev/null +++ b/ivtest/ivltests/case_mux_array_word.v @@ -0,0 +1,52 @@ +// Check that case statement muxes work with array word inputs. + +module test; + + reg [7:0] mem [0:3]; + reg [1:0] sel; + reg [7:0] out; + reg failed; + + `define check(val, exp) \ + if (val !== exp) begin \ + $display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \ + `"val`", exp, val); \ + failed = 1'b1; \ + end + + always @* begin + case (sel) + 2'd0: out = mem[0]; + 2'd1: out = mem[1]; + 2'd2: out = mem[2]; + 2'd3: out = mem[3]; + endcase + end + + (* ivl_synthesis_off *) + initial begin + failed = 1'b0; + + mem[0] = 8'h12; + mem[1] = 8'h34; + mem[2] = 8'h56; + mem[3] = 8'h78; + + sel = 2'd0; + #1 `check(out, 8'h12); + + sel = 2'd1; + #1 `check(out, 8'h34); + + sel = 2'd2; + #1 `check(out, 8'h56); + + sel = 2'd3; + #1 `check(out, 8'h78); + + if (!failed) begin + $display("PASSED"); + end + end + +endmodule diff --git a/ivtest/regress-vvp.list b/ivtest/regress-vvp.list index d9a8f3e7b..b516f9ce8 100644 --- a/ivtest/regress-vvp.list +++ b/ivtest/regress-vvp.list @@ -91,6 +91,7 @@ case1 vvp_tests/case1.json case2 vvp_tests/case2.json case2-S vvp_tests/case2-S.json case3 vvp_tests/case3.json +case_mux_array_word vvp_tests/case_mux_array_word.json casex_synth vvp_tests/casex_synth.json cast_int_ams vvp_tests/cast_int_ams.json cast_real_invalid1 vvp_tests/cast_real_invalid1.json diff --git a/ivtest/vvp_tests/case_mux_array_word.json b/ivtest/vvp_tests/case_mux_array_word.json new file mode 100644 index 000000000..b3303aeb1 --- /dev/null +++ b/ivtest/vvp_tests/case_mux_array_word.json @@ -0,0 +1,5 @@ +{ + "type" : "normal", + "source" : "case_mux_array_word.v", + "iverilog-args" : [ "-S" ] +}