From 148600814d3885ee9daa7179e015e3683948014d Mon Sep 17 00:00:00 2001
From: Stephen Williams <steve@icarus.com>
Date: Sat, 23 Jul 2011 10:44:36 -0700
Subject: [PATCH] Handle std_logic_vector library output stream

When writing arrays to the work library, handle the special
case that it is an array of std_logic and write a std_logic_vector
declaration instead. This makes for a more compact description.
---
 vhdlpp/vtype_stream.cc | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/vhdlpp/vtype_stream.cc b/vhdlpp/vtype_stream.cc
index b1d5d5735..2b2d70534 100644
--- a/vhdlpp/vtype_stream.cc
+++ b/vhdlpp/vtype_stream.cc
@@ -30,6 +30,17 @@ void VType::write_to_stream(ostream&fd) const
 
 void VTypeArray::write_to_stream(ostream&fd) const
 {
+	// Special case: std_logic_vector
+      if (etype_ == &primitive_STDLOGIC) {
+	    fd << "std_logic_vector";
+	    if (ranges_.size() > 0) {
+		  assert(ranges_.size() < 2);
+		  fd << " (" << ranges_[0].msb()
+		     << " downto " << ranges_[0].lsb() << ") ";
+	    }
+	    return;
+      }
+
       fd << "array ";
       if (ranges_.size() > 0) {
 	    assert(ranges_.size() < 2);