From 109c5d895d209049d1e459532b472d2aaa7560e0 Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Sat, 3 May 2014 15:45:15 -0700 Subject: [PATCH] Synthesis of assignment that is part of larger block. It is possible for an assignment statement to be part of a grander complex that has lots of outputs, not all handled by this particular assignment. In that case, the assignment may need to figure out which output it is supposed to bind to. --- synth2.cc | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/synth2.cc b/synth2.cc index 4057272b5..35362d1ee 100644 --- a/synth2.cc +++ b/synth2.cc @@ -136,10 +136,21 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope, rsig = tmp; } - ivl_assert(*this, nex_out.pin_count()==1); - ivl_assert(*this, rsig->pin_count()==1); - connect(nex_out.pin(0), rsig->pin(0)); + if (nex_out.pin_count() > 1) { + NexusSet tmp_set; + nex_output(tmp_set); + ivl_assert(*this, tmp_set.size()==1); + unsigned ptr = nex_map.find_nexus(tmp_set[0]); + ivl_assert(*this, rsig->pin_count()==1); + ivl_assert(*this, nex_map.size()==nex_out.pin_count()); + ivl_assert(*this, nex_out.pin_count() > ptr); + connect(nex_out.pin(ptr), rsig->pin(0)); + } else { + ivl_assert(*this, nex_out.pin_count()==1); + ivl_assert(*this, rsig->pin_count()==1); + connect(nex_out.pin(0), rsig->pin(0)); + } /* This lval_ represents a reg that is a WIRE in the synthesized results. This function signals the destructor