From 0fa223434e8718c9bc5028b715a87fd0535d1c73 Mon Sep 17 00:00:00 2001
From: Cary R <cygcary@yahoo.com>
Date: Wed, 16 Jan 2008 10:51:32 -0800
Subject: [PATCH] Add check target to tgt-verilog/Makefile.in

Add the missing check target to Makefile.in.
---
 tgt-verilog/Makefile.in | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tgt-verilog/Makefile.in b/tgt-verilog/Makefile.in
index aee582948..eac3269e7 100644
--- a/tgt-verilog/Makefile.in
+++ b/tgt-verilog/Makefile.in
@@ -70,6 +70,8 @@ clean:
 distclean: clean
 	rm -f Makefile
 
+check: all
+
 install: all installdirs $(libdir)/ivl/verilog.tgt \
 	$(includedir)/vpi_user.h