luke/iverilog
1
0
Fork 0
mirror of https://github.com/steveicarus/iverilog.git synced 2026-08-22 05:47:31 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix for GitHub issue #103 - vvp assertion failure on part select propagation.

Browse Source 
The implementation of vvp_fun_part_pv::recv_vec4_pv was incorrect, and
propagated the incoming widths rather than the stored widths.

(cherry picked from commit 0c66116f51)
This commit is contained in:
Martin Whitaker
2016-05-10 22:41:58 +01:00
parent 30257e0914
commit 06f6a72770
1 changed files with 8 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
vvp/part.cc
+8 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2004-2014 Stephen Williams ([email protected])
* Copyright (c) 2004-2016 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -213,8 +213,14 @@ void vvp_fun_part_pv::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
vvp_context_t ctx)
{
assert(port.port() == 0);
assert(bit.size() == wid);
assert(base + wid <= vwid);
assert(vwid == wid_);
port.ptr()->send_vec4_pv(bit, base, wid, vwid, ctx);
vvp_vector4_t tmp(wid_, BIT4_Z);
tmp.set_vec(base, bit);
port.ptr()->send_vec4_pv(tmp, base_, wid_, vwid_, ctx);
}
void vvp_fun_part_pv::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit)