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For SystemVerilog, support localparam in module parameter port lists.

This commit is contained in:
Martin Whitaker 2019-10-06 08:44:51 +01:00
parent 763cc9c162
commit 06a60cac01
1 changed files with 19 additions and 7 deletions
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26
parse.y
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@ -4890,15 +4890,27 @@ module_port_list_opt
ports. These are simply advance ways to declare parameters, so ports. These are simply advance ways to declare parameters, so
that the port declarations may use them. */ that the port declarations may use them. */
module_parameter_port_list_opt module_parameter_port_list_opt
: :
| '#' '(' module_parameter_port_list ')' | '#' '(' module_parameter_port_list ')'
; ;
module_parameter_port_list module_parameter_port_list
: K_parameter param_type parameter_assign : K_parameter param_type parameter_assign
| module_parameter_port_list ',' parameter_assign | K_localparam param_type localparam_assign
| module_parameter_port_list ',' K_parameter param_type parameter_assign { if (!gn_system_verilog()) {
; yyerror(@1, "error: Local parameters in module parameter "
"port lists requires SystemVerilog.");
}
}
| module_parameter_port_list ',' parameter_assign
| module_parameter_port_list ',' K_parameter param_type parameter_assign
| module_parameter_port_list ',' K_localparam param_type localparam_assign
{ if (!gn_system_verilog()) {
yyerror(@3, "error: Local parameters in module parameter "
"port lists requires SystemVerilog.");
}
}
;
module_item module_item