From 06a60cac01ec3e6e85e5fc055478b3befb709201 Mon Sep 17 00:00:00 2001
From: Martin Whitaker <icarus@martin-whitaker.me.uk>
Date: Sun, 6 Oct 2019 08:44:51 +0100
Subject: [PATCH] For SystemVerilog, support localparam in module parameter
 port lists.

---
 parse.y | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/parse.y b/parse.y
index e0152f763..86d5de910 100644
--- a/parse.y
+++ b/parse.y
@@ -4890,15 +4890,27 @@ module_port_list_opt
      ports. These are simply advance ways to declare parameters, so
      that the port declarations may use them. */
 module_parameter_port_list_opt
-	:
-        | '#' '(' module_parameter_port_list ')'
-	;
+  :
+  | '#' '(' module_parameter_port_list ')'
+  ;
 
 module_parameter_port_list
-	: K_parameter param_type parameter_assign
-	| module_parameter_port_list ',' parameter_assign
-	| module_parameter_port_list ',' K_parameter param_type parameter_assign
-	;
+  : K_parameter param_type parameter_assign
+  | K_localparam param_type localparam_assign
+      { if (!gn_system_verilog()) {
+	      yyerror(@1, "error: Local parameters in module parameter "
+			  "port lists requires SystemVerilog.");
+	}
+      }
+  | module_parameter_port_list ',' parameter_assign
+  | module_parameter_port_list ',' K_parameter param_type parameter_assign
+  | module_parameter_port_list ',' K_localparam param_type localparam_assign
+      { if (!gn_system_verilog()) {
+	      yyerror(@3, "error: Local parameters in module parameter "
+			  "port lists requires SystemVerilog.");
+	}
+      }
+  ;
 
 module_item