luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Space/code cleanup and warn that vvp does not support S/R D-FF

This commit is contained in:
Cary R 2015-04-20 15:40:10 -07:00
parent f9fef5d00b
commit 02ee3874e7
3 changed files with 45 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
link_const.cc
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2015 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@ -282,8 +282,7 @@ vector<bool> Nexus::driven_mask(void) const
for (size_t idx = 0 ; idx < mask.size() ; idx += 1)
mask[idx] = true;
return mask;
}
else {
} else {
if (cur->get_pin() != 1)
continue;
}

28
synth2.cc
View File

@ -206,7 +206,6 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope,
<< " Found no use_sig, resorting to lsig." << endl;
}
}
//this substitutes the part of the use_lsig with rsig..
NetSubstitute*ps = new NetSubstitute(use_lsig, rsig,
tmp->vector_width(),
base_off);
@ -1550,23 +1549,29 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope,
connect(ff_aset.pin(pin), rst->pin(0));
} else {
NetConcat * set_cc=new NetConcat(scope, scope->local_symbol(),
rst_nex->vector_width(), rst_drv.len(), true);
NetConcat * rst_cc=new NetConcat(scope, scope->local_symbol(),
rst_nex->vector_width(), rst_drv.len(), true);
NetConcat *set_cc = new NetConcat(scope,
scope->local_symbol(),
rst_nex->vector_width(),
rst_drv.len(), true);
NetConcat *rst_cc = new NetConcat(scope,
scope->local_symbol(),
rst_nex->vector_width(),
rst_drv.len(), true);
ivl_variable_type_t oosig_data_type = IVL_VT_LOGIC;
netvector_t *oosig_vec = new netvector_t(oosig_data_type, 0, 0);
NetNet*oosig[2] = {new NetNet(scope, scope->local_symbol(),
NetNet::TRI, oosig_vec),new NetNet(scope, scope->local_symbol(),
NetNet *oosig[2] = {new NetNet(scope,
scope->local_symbol(),
NetNet::TRI, oosig_vec),
new NetNet(scope,
scope->local_symbol(),
NetNet::TRI, oosig_vec)};
int i;
set_cc->set_line(*this);
des->add_node(set_cc);
connect(set_cc->pin(0), oosig[0]->pin(0));
rst_cc->set_line(*this);
des->add_node(rst_cc);
connect(rst_cc->pin(0), oosig[1]->pin(0));
for(i=0;i<(int)rst_drv.len();i++) {
for (int i = 0; i < (int)rst_drv.len(); i += 1) {
// This is the output signal f const, osig.
ivl_variable_type_t osig_data_type = IVL_VT_LOGIC;
netvector_t*osig_vec = new netvector_t(osig_data_type, 0, 0);
@ -1580,8 +1585,7 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope,
if (rst_drv[i] == verinum::V1) {
connect(set_cc->pin(i+1), rst->pin(0));
connect(rst_cc->pin(i+1), nc->pin(0));
}
else {
} else {
connect(set_cc->pin(i+1), nc->pin(0));
connect(rst_cc->pin(i+1), rst->pin(0));
}
@ -1778,7 +1782,6 @@ bool NetEvWait::synth_sync(Design*des, NetScope*scope,
assert(ev->nprobe() >= 1);
vector<NetEvProbe*>events (ev->nprobe() - 1);
// vector<NetEvProbe*>events (ev->nprobe());
/* Get the input set from the substatement. This will be used
to figure out which of the probes is the clock. */
@ -1806,7 +1809,6 @@ bool NetEvWait::synth_sync(Design*des, NetScope*scope,
pclk = tmp;
} else {
// assert(events.size() > event_idx);
events[event_idx++] = tmp;
}
}

8
tgt-vvp/vvp_scope.c
View File

@ -1737,10 +1737,14 @@ static void draw_lpm_ff(ivl_lpm_t net)
assert(ivl_lpm_sync_set(net) == 0);
if (ivl_lpm_async_clr(net)) {
assert(! ivl_lpm_async_set(net));
if (ivl_lpm_async_set(net)) {
fprintf(stderr, "%s:%u:vvp.tgt: sorry: No support for a D-ff "
"with both an async. set and clear.\n",
ivl_lpm_file(net), ivl_lpm_lineno(net));
vvp_errors += 1;
}
fprintf(vvp_out, "L_%p .dff/aclr ", net);
} else if (ivl_lpm_async_set(net)) {
assert(! ivl_lpm_async_clr(net));
fprintf(vvp_out, "L_%p .dff/aset ", net);
} else {
fprintf(vvp_out, "L_%p .dff ", net);