diff --git a/link_const.cc b/link_const.cc index 86db02760..e28388bbf 100644 --- a/link_const.cc +++ b/link_const.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2000-2014 Stephen Williams (steve@icarus.com) + * Copyright (c) 2000-2015 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU @@ -277,14 +277,13 @@ vector Nexus::driven_mask(void) const const NetPartSelect*obj_ps = dynamic_cast(obj); if(obj_ps) { if (obj_ps->dir()==NetPartSelect::VP) { - if(cur->get_pin()!=0) + if(cur->get_pin() != 0) continue; for (size_t idx = 0 ; idx < mask.size() ; idx += 1) mask[idx] = true; return mask; - } - else { - if (cur->get_pin()!=1) + } else { + if (cur->get_pin() != 1) continue; } for (unsigned idx = 0 ; idx < obj_ps->width() ; idx += 1) { diff --git a/synth2.cc b/synth2.cc index 8ee1bff49..96c8208e6 100644 --- a/synth2.cc +++ b/synth2.cc @@ -100,15 +100,15 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope, << ", nex_out.pin_count()==" << nex_out.pin_count() << endl; } - if(lval_->more ) { - unsigned base=0,width=1; - unsigned i=0; - NetAssign_ *lval=lval_; - while(lval) { + if (lval_->more ) { + unsigned base = 0, width = 1; + unsigned i = 0; + NetAssign_ *lval = lval_; + while (lval) { NetNet *llsig = lval->sig(); - width=lval->lwidth(); + width = lval->lwidth(); ivl_variable_type_t tmp_data_type = llsig->data_type(); - netvector_t *tmp_type = new netvector_t(tmp_data_type, llsig->vector_width()-1,0); + netvector_t *tmp_type = new netvector_t(tmp_data_type, llsig->vector_width()-1, 0); NetNet *tmp = new NetNet(scope, scope->local_symbol(), NetNet::WIRE, NetNet::not_an_array, tmp_type); @@ -117,13 +117,13 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope, ps->set_line(*this); des->add_node(ps); - connect(tmp->pin(0),ps->pin(0)); + connect(tmp->pin(0), ps->pin(0)); connect(nex_out.pin(i), tmp->pin(0)); - base+=width; + base += width; i++; lval->turn_sig_to_wire_on_release(); - lval=lval->more; + lval = lval->more; } return true; } @@ -206,7 +206,6 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope, << " Found no use_sig, resorting to lsig." << endl; } } -//this substitutes the part of the use_lsig with rsig.. NetSubstitute*ps = new NetSubstitute(use_lsig, rsig, tmp->vector_width(), base_off); @@ -1550,44 +1549,49 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope, connect(ff_aset.pin(pin), rst->pin(0)); } else { - NetConcat * set_cc=new NetConcat(scope, scope->local_symbol(), - rst_nex->vector_width(), rst_drv.len(), true); - NetConcat * rst_cc=new NetConcat(scope, scope->local_symbol(), - rst_nex->vector_width(), rst_drv.len(), true); + NetConcat *set_cc = new NetConcat(scope, + scope->local_symbol(), + rst_nex->vector_width(), + rst_drv.len(), true); + NetConcat *rst_cc = new NetConcat(scope, + scope->local_symbol(), + rst_nex->vector_width(), + rst_drv.len(), true); ivl_variable_type_t oosig_data_type = IVL_VT_LOGIC; - netvector_t*oosig_vec = new netvector_t(oosig_data_type, 0, 0); - NetNet*oosig[2] = {new NetNet(scope, scope->local_symbol(), - NetNet::TRI, oosig_vec),new NetNet(scope, scope->local_symbol(), - NetNet::TRI, oosig_vec)}; - int i; + netvector_t *oosig_vec = new netvector_t(oosig_data_type, 0, 0); + NetNet *oosig[2] = {new NetNet(scope, + scope->local_symbol(), + NetNet::TRI, oosig_vec), + new NetNet(scope, + scope->local_symbol(), + NetNet::TRI, oosig_vec)}; set_cc->set_line(*this); des->add_node(set_cc); - connect(set_cc->pin(0),oosig[0]->pin(0)); + connect(set_cc->pin(0), oosig[0]->pin(0)); rst_cc->set_line(*this); des->add_node(rst_cc); - connect(rst_cc->pin(0),oosig[1]->pin(0)); - for(i=0;i<(int)rst_drv.len();i++) { + connect(rst_cc->pin(0), oosig[1]->pin(0)); + for (int i = 0; i < (int)rst_drv.len(); i += 1) { // This is the output signal f const, osig. ivl_variable_type_t osig_data_type = IVL_VT_LOGIC; netvector_t*osig_vec = new netvector_t(osig_data_type, 0, 0); - NetNet*osig = new NetNet(scope, scope->local_symbol(), + NetNet *osig = new NetNet(scope, scope->local_symbol(), NetNet::TRI, osig_vec); - NetConst * nc = new NetConst(scope, scope->local_symbol(), + NetConst *nc = new NetConst(scope, scope->local_symbol(), verinum(verinum::V0, 1)); - connect(nc->pin(0),osig->pin(0)); + connect(nc->pin(0), osig->pin(0)); nc->set_line(*this); des->add_node(nc); - if(rst_drv[i]==verinum::V1) { + if (rst_drv[i] == verinum::V1) { connect(set_cc->pin(i+1), rst->pin(0)); connect(rst_cc->pin(i+1), nc->pin(0)); - } - else { + } else { connect(set_cc->pin(i+1), nc->pin(0)); connect(rst_cc->pin(i+1), rst->pin(0)); } } - connect(ff_aset.pin(pin),set_cc->pin(0)); - connect(ff_aclr.pin(pin),rst_cc->pin(0)); + connect(ff_aset.pin(pin), set_cc->pin(0)); + connect(ff_aclr.pin(pin), rst_cc->pin(0)); } } @@ -1778,7 +1782,6 @@ bool NetEvWait::synth_sync(Design*des, NetScope*scope, assert(ev->nprobe() >= 1); vectorevents (ev->nprobe() - 1); -// vectorevents (ev->nprobe()); /* Get the input set from the substatement. This will be used to figure out which of the probes is the clock. */ @@ -1806,7 +1809,6 @@ bool NetEvWait::synth_sync(Design*des, NetScope*scope, pclk = tmp; } else { -// assert(events.size() > event_idx); events[event_idx++] = tmp; } } diff --git a/tgt-vvp/vvp_scope.c b/tgt-vvp/vvp_scope.c index b1bfb33d1..44d5b1e53 100644 --- a/tgt-vvp/vvp_scope.c +++ b/tgt-vvp/vvp_scope.c @@ -1737,10 +1737,14 @@ static void draw_lpm_ff(ivl_lpm_t net) assert(ivl_lpm_sync_set(net) == 0); if (ivl_lpm_async_clr(net)) { - assert(! ivl_lpm_async_set(net)); + if (ivl_lpm_async_set(net)) { + fprintf(stderr, "%s:%u:vvp.tgt: sorry: No support for a D-ff " + "with both an async. set and clear.\n", + ivl_lpm_file(net), ivl_lpm_lineno(net)); + vvp_errors += 1; + } fprintf(vvp_out, "L_%p .dff/aclr ", net); } else if (ivl_lpm_async_set(net)) { - assert(! ivl_lpm_async_clr(net)); fprintf(vvp_out, "L_%p .dff/aset ", net); } else { fprintf(vvp_out, "L_%p .dff ", net);