More examples.

examples/.cvsignore

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+,*
+hello_vpi.vpi
+show_vcd.vcd

examples/hello_vpi.c

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+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#ident "$Id: hello_vpi.c,v 1.1 2002/04/18 03:25:16 steve Exp $"
+
+/*
+ * This file contains an example VPI module to demonstrate the tools
+ * to create vpi modules. To compile this module, use the iverilog-vpi
+ * command like so:
+ *
+ *    iverilog-vpi hello_vpi.c
+ *
+ * The result is the hello_vpi.vpi module. See the hello_vpi.vl
+ * program for example Verilog code to call this module.
+ */
+
+# include  <vpi_user.h>
+
+static int my_hello_calltf(char *xx)
+{
+      vpi_printf("Hello World, from VPI.\n");
+      return 0;
+}
+
+static void my_hello_register()
+{
+      s_vpi_systf_data tf_data;
+
+      tf_data.type      = vpiSysTask;
+      tf_data.tfname    = "$my_hello";
+      tf_data.calltf    = my_hello_calltf;
+      tf_data.compiletf = 0;
+      tf_data.sizetf    = 0;
+      vpi_register_systf(&tf_data);
+
+}
+
+/*
+ * This is a table of register functions. This table is the external
+ * symbol that the simulator looks for when loading this .vpi module.
+ */
+void (*vlog_startup_routines[])() = {
+      my_hello_register,
+      0
+};
+/*
+ * $Log: hello_vpi.c,v $
+ * Revision 1.1  2002/04/18 03:25:16  steve
+ *  More examples.
+ *
+ */
+

examples/hello_vpi.vl

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+/*
+ * Copyright (c) 2002 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+ /*
+  *  Here we have the canonical "Hello, World" program written in Verilog,
+  *  with VPI. It uses the hello_vpi.vpi module that is compiled from
+  *  the hello_vpi.c program also in this directory. See the
+  *  hello_vpi.c for instructions on how to compile it.
+  *
+  *  Compile this program with the command:
+  *
+  *      iverilog -ohello_vpi hello_vpi.vl
+  *  
+  *  After churning for a little while, the program will create the output
+  *  file "hello" which is compiled, linked and ready to run. Run this
+  *  program like so:
+  *  
+  *      vvp -M. -mhello_vpi hello_vpi
+  *  
+  *  and the program will print the message to its output. Easy! For
+  *  more on how to make the iverilog command work, see the iverilog
+  *  manual page.
+  */
+
+module main();
+ 
+initial 
+  begin
+     $my_hello;
+     $finish ;
+  end
+
+endmodule

examples/xram16x1.v

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+/*
+ * Copyright (c) 1999 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+// This example describes a 16x1 RAM that can be synthesized into
+// a CLB ram in a Xilinx FPGA.
+
+module ram16x1 (q, d, a, we, wclk);
+   output q;
+   input d;
+   input [3:0] a;
+   input we;
+   input wclk;
+
+   reg mem[15:0];
+   
+   assign q = mem[a];
+   always @(posedge wclk) if (we) mem[a] = d;
+
+endmodule /* ram16x1 */
+
+module main;
+   wire q;
+   reg d;
+   reg [3:0] a;
+   reg we, wclk;
+    
+   ram16x1 r1 (q, d, a, we, wclk);
+
+   initial begin
+      $monitor("q = %b", q);
+      d = 0;
+      wclk = 0;
+      a = 5;
+      we = 1;
+      #1 wclk = 1;
+      #1 wclk = 0;
+   end
+endmodule /* main */