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iverilog/docs/ROADMAP.md

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UVM track: seed uvm/, docs, and hello_uvm example Standalone muhammadjawadkhan/iverilog-uvm project setup. Documents that this fork is experimental and must not PR UVM work to steveicarus/iverilog. Seeds uvm/ from IVL_UVM and adds roadmap/status workflow docs plus a smoke example.
2026-07-21 13:14:00 +02:00
# Feature roadmap (one-by-one)
Each item should be a dedicated `feat/<name>` branch, with tests/examples and a STATUS.md update. Merge only into this fork’s default branch (`master`).
## Tier A — Compiler SV foundations (block Accellera UVM)
SV: add string-keyed associative array vertical slice Support int aa[string]/int aa[*] with assign, size/num, exists, delete, foreach, and whole-array copy for UVM Tier A table patterns. Runtime uses vvp_aarray_vec4 (std::map); int keys and richer element types deferred.
2026-07-21 14:12:16 +02:00
1. **Parameterized classes** — `class C #(type T = int);` / `C#(byte)` — needed for `uvm_*#(T)`, `config_db` — **partial** (defaults; see STATUS)
2. **Associative arrays** — `int aa[string];` — **in progress / partial** (string keys only; see [assoc-array.md](assoc-array.md))
SV: add virtual-interface vertical slice for UVM agents Support virtual interface class properties/TF args, instance bind, member R/W, and @(posedge vif.clk) so basic driver connectivity works.
2026-07-21 14:58:35 +02:00
3. **Virtual interfaces** + eventing on `vif.clk` — **partial** (see [virtual-interface.md](virtual-interface.md))
SV: add interface clocking-block vertical slice for UVM Parse interface-local clocking blocks, treat cb as a transparent hop for member R/W, and elaborate @(bif.cb) as the clocking event so basic driver sync works with #0 skew.
2026-07-21 15:16:16 +02:00
4. **Clocking blocks** — enough for `@(vif.cb)` — **partial** (interface-local `@(bif.cb)`; see [clocking.md](clocking.md))
SV: add mailbox/semaphore builtins for UVM IPC Implement native SystemVerilog mailbox and semaphore with blocking and nonblocking put/get, so Accellera-style code can use the standard API without depending on the legacy IVL_UVM poor-man's classes.
2026-07-21 15:37:08 +02:00
5. **`mailbox` / `semaphore` builtins** (or solid class equivalents with blocking put/get) — **partial** (int mailbox + semaphore; see [mailbox-semaphore.md](mailbox-semaphore.md))
UVM track: seed uvm/, docs, and hello_uvm example Standalone muhammadjawadkhan/iverilog-uvm project setup. Documents that this fork is experimental and must not PR UVM work to steveicarus/iverilog. Seeds uvm/ from IVL_UVM and adds roadmap/status workflow docs plus a smoke example.
2026-07-21 13:14:00 +02:00
6. **Constraints + `randomize()` / `randomize() with`** — start unconstrained `rand`, then solver
7. **`$cast` / `$typename` hardening** for factory patterns
8. **Covergroups** — functional coverage
9. **DPI-C** — optional but common in real flows
## Tier B — Library / methodology (on top of Tier A)
10. Grow [`uvm/`](../uvm/) toward Accellera-shaped APIs: reporting, phases/objections, factory, `config_db`, TLM, sequences
11. Smoke: trimmed “hello UVM”, then larger Accellera UVM 1.2 slices as features land
## Already usable baseline (do not re-do first)
Classes, packages, strings, queues/dynamic arrays, locators/reductions/ordering, chained calls — extend only when a UVM example needs a gap.
## Out of scope
- Claiming “UVM 1.2 supported” until Accellera’s library compiles and runs
- Opening PRs to `steveicarus/iverilog` for this track (see [WORKFLOW.md](WORKFLOW.md))