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iverilog/vhdlpp/main.cc

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Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
const char COPYRIGHT[] =
Handle prefix expressions that include array index expressions.
2012-09-01 23:51:04 +02:00
"Copyright (c) 2011-2012 Stephen Williams (steve@icarus.com)\n"
"Copyright CERN 2012 / Stephen Williams (steve@icarus.com)";
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
/*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
updated FSF-address
2012-08-29 03:41:23 +02:00
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
*/
# include "vhdlpp_config.h"
# include "version_base.h"
# include "version_tag.h"
Add +vhdl-work+ control to the config file. Presumably, the user will want the ability to explicitly set the working library location, so create a +vhdl-work+ plusarg setting for exactly that purpose.
2011-07-25 00:24:32 +02:00
/*
* Usage: vhdlpp [flags] sourcefile...
* Flags:
*
** -D <token>
* This activates various sorts of debugging aids. The <token>
* specifies which debugging aid to activate. Valid tokens are:
*
* yydebug | no-yydebug
* Enable (disable) debug prints from the bison parser
*
* libraries=<path>
* Enable debugging of library support by dumping library
* information to the file named <path>.
*
Handle prefix expressions that include array index expressions.
2012-09-01 23:51:04 +02:00
* elaboration=<path>
* Enable debugging of elaboratin by dumping elaboration
* process information to the file named <path>.
*
Add +vhdl-work+ control to the config file. Presumably, the user will want the ability to explicitly set the working library location, so create a +vhdl-work+ plusarg setting for exactly that purpose.
2011-07-25 00:24:32 +02:00
* entities=<path>
* Enable debugging of elaborated entities by writing the
* elaboration results to the file named <path>.
*
** -v
* Verbose operation. Display verbose non-debug information.
*
** -V
* Version. Print the version of this binary.
*
** -w <path>
* Work path. This sets the path to the working library
* directory. I write into that directory files for packages that
* I declare, and I read from that directory packages that are
* already declared. The default path is "ivl_vhdl_work".
*/
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
const char NOTICE[] =
" This program is free software; you can redistribute it and/or modify\n"
" it under the terms of the GNU General Public License as published by\n"
" the Free Software Foundation; either version 2 of the License, or\n"
" (at your option) any later version.\n"
"\n"
" This program is distributed in the hope that it will be useful,\n"
" but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"
" GNU General Public License for more details.\n"
"\n"
" You should have received a copy of the GNU General Public License along\n"
" with this program; if not, write to the Free Software Foundation, Inc.,\n"
" 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.\n"
;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
# include "compiler.h"
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
# include "parse_api.h"
Create the shell of a proper type system. Rather then just relying on comparing type names all throughout elaboration, create type description data structures and use them during elaboration to handle proper types.
2011-02-07 05:55:31 +01:00
# include "vtype.h"
Add support for constants and package types. Significant rework of scope management to unify the handling of types in the ieee library and types/constants/components in packages. This involved adjusting the parser rules to manage a stack of scopes and rewriting the IEEE library support to not use global maps for the loaded types.
2011-04-18 02:19:09 +02:00
# include <fstream>
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
# include <cstdio>
# include <cstdlib>
# include <cstring>
Write package headers to a library file Build up a work library by writing a VHDL representation of the package header into a source file. This representation needs to be accurate enough that later invocations of vhdlpp can read them with the VHDL parser.
2011-07-20 04:19:27 +02:00
# include <cerrno>
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
#if defined(HAVE_GETOPT_H)
# include <getopt.h>
#endif
Write package headers to a library file Build up a work library by writing a VHDL representation of the package header into a source file. This representation needs to be accurate enough that later invocations of vhdlpp can read them with the VHDL parser.
2011-07-20 04:19:27 +02:00
# include <sys/stat.h>
Use mkdir() instead of _mkdir() for MinGW MinGW-w64 requires the use of mkdir() and MinGW-w32 appears to support both so use mkdir() to allow compilation to work with both versions.
2011-12-18 20:41:21 +01:00
// MinGW only supports mkdir() with a path. If this stops working because
// we need to use _mkdir() for mingw-w32 and mkdir() for mingw-w64 look
// at using the autoconf AX_FUNC_MKDIR macro to figure this all out.
Compiler fixes for MinGW. In MinGW, when parameters are passed to vhdlpp by ivlpp, single quotes are treated as ordinary characters. Use double quotes instead, as is done in the driver. Also, MinGW does not have a standard mkdir() function, so we need to convert calls to mkdir() into calls to _mkdir().
2011-11-02 21:09:42 +01:00
#if defined(__MINGW32__)
# include <io.h>
Use mkdir() instead of _mkdir() for MinGW MinGW-w64 requires the use of mkdir() and MinGW-w32 appears to support both so use mkdir() to allow compilation to work with both versions.
2011-12-18 20:41:21 +01:00
# define mkdir(path, mode) mkdir(path)
Compiler fixes for MinGW. In MinGW, when parameters are passed to vhdlpp by ivlpp, single quotes are treated as ordinary characters. Use double quotes instead, as is done in the driver. Also, MinGW does not have a standard mkdir() function, so we need to convert calls to mkdir() into calls to _mkdir().
2011-11-02 21:09:42 +01:00
#endif
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
Add VHDLPP support to ivlpp program The ivlpp program is a good place to detect that the source file is VHDL, and pass the source file to the vhdlpp program. Do so automatically.
2010-12-19 12:33:04 +01:00
bool verbose_flag = false;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
// Where to dump design entities
const char*dump_design_entities_path = 0;
Add support for constants and package types. Significant rework of scope management to unify the handling of types in the ieee library and types/constants/components in packages. This involved adjusting the parser rules to manage a stack of scopes and rewriting the IEEE library support to not use global maps for the loaded types.
2011-04-18 02:19:09 +02:00
const char*dump_libraries_path = 0;
Handle prefix expressions that include array index expressions.
2012-09-01 23:51:04 +02:00
const char*debug_log_path = 0;
Add support for constants and package types. Significant rework of scope management to unify the handling of types in the ieee library and types/constants/components in packages. This involved adjusting the parser rules to manage a stack of scopes and rewriting the IEEE library support to not use global maps for the loaded types.
2011-04-18 02:19:09 +02:00
Handle prefix expressions that include array index expressions.
2012-09-01 23:51:04 +02:00
bool debug_elaboration = false;
ofstream debug_log_file;
Write package headers to a library file Build up a work library by writing a VHDL representation of the package header into a source file. This representation needs to be accurate enough that later invocations of vhdlpp can read them with the VHDL parser.
2011-07-20 04:19:27 +02:00
Add support for constants and package types. Significant rework of scope management to unify the handling of types in the ieee library and types/constants/components in packages. This involved adjusting the parser rules to manage a stack of scopes and rewriting the IEEE library support to not use global maps for the loaded types.
2011-04-18 02:19:09 +02:00
extern void dump_libraries(ostream&file);
Add parser cleanup to vhdlpp This commit adds removal of global objects in the execution of vhdlpp. This includes deleting design entities and the global parse scope.
2011-07-20 18:19:48 +02:00
extern void parser_cleanup();
Add VHDLPP support to ivlpp program The ivlpp program is a good place to detect that the source file is VHDL, and pass the source file to the vhdlpp program. Do so automatically.
2010-12-19 12:33:04 +01:00
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
static void process_debug_token(const char*word)
{
if (strcmp(word, "yydebug") == 0) {
yydebug = 1;
} else if (strcmp(word, "no-yydebug") == 0) {
yydebug = 0;
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
} else if (strncmp(word, "entities=", 9) == 0) {
dump_design_entities_path = strdup(word+9);
Add support for constants and package types. Significant rework of scope management to unify the handling of types in the ieee library and types/constants/components in packages. This involved adjusting the parser rules to manage a stack of scopes and rewriting the IEEE library support to not use global maps for the loaded types.
2011-04-18 02:19:09 +02:00
} else if (strncmp(word, "libraries=", 10) == 0) {
dump_libraries_path = strdup(word+10);
Handle prefix expressions that include array index expressions.
2012-09-01 23:51:04 +02:00
} else if (strncmp(word, "log=", 4) == 0) {
debug_log_path = strdup(word+4);
} else if (strcmp(word, "elaboration") == 0) {
debug_elaboration = true;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
}
}
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
int main(int argc, char*argv[])
{
int opt;
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
int rc;
Write package headers to a library file Build up a work library by writing a VHDL representation of the package header into a source file. This representation needs to be accurate enough that later invocations of vhdlpp can read them with the VHDL parser.
2011-07-20 04:19:27 +02:00
const char*work_path = "ivl_vhdl_work";
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
Add VHDL support for named libraries Named libraries are similar to the work library, but they are not written to implicitly, or imported implicitly. They are only brought in by a "library" clause, the the packages within the library are brought in by a "use" clause.
2011-07-31 00:04:07 +02:00
while ( (opt=getopt(argc, argv, "D:L:vVw:")) != EOF) switch (opt) {
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
case 'D':
process_debug_token(optarg);
break;
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
Add VHDL support for named libraries Named libraries are similar to the work library, but they are not written to implicitly, or imported implicitly. They are only brought in by a "library" clause, the the packages within the library are brought in by a "use" clause.
2011-07-31 00:04:07 +02:00
case 'L':
library_add_directory(optarg);
break;
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
case 'v':
fprintf(stderr, "Icarus Verilog VHDL Parse version "
VERSION " (" VERSION_TAG ")\n\n");
fprintf(stderr, "%s\n\n", COPYRIGHT);
fputs(NOTICE, stderr);
Add VHDLPP support to ivlpp program The ivlpp program is a good place to detect that the source file is VHDL, and pass the source file to the vhdlpp program. Do so automatically.
2010-12-19 12:33:04 +01:00
verbose_flag = true;
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
break;
case 'V':
fprintf(stdout, "Icarus Verilog VHDL Parse version "
VERSION " (" VERSION_TAG ")\n\n");
fprintf(stdout, "%s\n\n", COPYRIGHT);
fputs(NOTICE, stdout);
break;
Write package headers to a library file Build up a work library by writing a VHDL representation of the package header into a source file. This representation needs to be accurate enough that later invocations of vhdlpp can read them with the VHDL parser.
2011-07-20 04:19:27 +02:00
case 'w':
work_path = optarg;
break;
}
Handle prefix expressions that include array index expressions.
2012-09-01 23:51:04 +02:00
if (debug_log_path) {
debug_log_file.open(debug_log_path);
}
Write package headers to a library file Build up a work library by writing a VHDL representation of the package header into a source file. This representation needs to be accurate enough that later invocations of vhdlpp can read them with the VHDL parser.
2011-07-20 04:19:27 +02:00
if ( (rc = mkdir(work_path, 0777)) < 0 ) {
if (errno != EEXIST) {
fprintf(stderr, "Icarus Verilog VHDL unable to create work directory %s, errno=%d\n", work_path, errno);
return -1;
}
struct stat stat_buf;
rc = stat(work_path, &stat_buf);
if (!S_ISDIR(stat_buf.st_mode)) {
fprintf(stderr, "Icarus Verilog VHDL work path `%s' is not a directory.\n", work_path);
return -1;
}
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
}
Write package headers to a library file Build up a work library by writing a VHDL representation of the package header into a source file. This representation needs to be accurate enough that later invocations of vhdlpp can read them with the VHDL parser.
2011-07-20 04:19:27 +02:00
library_set_work_path(work_path);
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
preload_global_types();
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
int errors = 0;
Do type mapping in the parser. In VHDL, types are declared before they are used, so it is possible to do type binding during parse. This makes the parser a little bit cleaner.
2011-02-14 01:37:10 +01:00
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
for (int idx = optind ; idx < argc ; idx += 1) {
parse_errors = 0;
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
parse_sorrys = 0;
Add VHDL support for named libraries Named libraries are similar to the work library, but they are not written to implicitly, or imported implicitly. They are only brought in by a "library" clause, the the packages within the library are brought in by a "use" clause.
2011-07-31 00:04:07 +02:00
rc = parse_source_file(argv[idx], perm_string());
Parse work library for imported packages When a "use" clause tries to pull a package from the work library, put together a file name and try to find that package in the work library directory. If found, parse the package file and try again to find the package.
2011-07-23 19:07:20 +02:00
if (rc < 0)
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
return 1;
Rework parse/lex API to be reentrant Bison and Flex generate different interfaces for reentrant parsers, so handle that different API. We need this change because library support is going to reuse the parser to read in library packages.
2011-07-23 05:49:57 +02:00
Add VHDLPP support to ivlpp program The ivlpp program is a good place to detect that the source file is VHDL, and pass the source file to the vhdlpp program. Do so automatically.
2010-12-19 12:33:04 +01:00
if (verbose_flag)
Parse work library for imported packages When a "use" clause tries to pull a package from the work library, put together a file name and try to find that package in the work library directory. If found, parse the package file and try again to find the package.
2011-07-23 19:07:20 +02:00
fprintf(stderr, "parse_source_file() returns %d, parse_errors=%d, parse_sorrys=%d\n", rc, parse_errors, parse_sorrys);
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
if (parse_errors > 0) {
Add parser support for architecture declaratives and component instantiations Also include support for "sorry" messages so that we have a place to hang unsupported but properly parsed constructs. In the process of doing this, I also encountered and add parser support for indexed names. And matching "sorry" messages.
2011-03-20 02:26:43 +01:00
fprintf(stderr, "Encountered %d errors parsing %s\n", parse_errors, argv[idx]);
}
if (parse_sorrys > 0) {
fprintf(stderr, "Encountered %d unsupported constructs parsing %s\n", parse_sorrys, argv[idx]);
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
}
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
if (parse_errors || parse_sorrys) {
errors += parse_errors;
errors += parse_sorrys;
break;
}
Flesh out VHDL parser engine. Add enough rules to parse a simple VHDL program: Parse library and use clauses, Parse entity declarations, and Parse architecture bodies. Add some parser infrastructure: Handle syntax errors with useful error messages, Include file name and line numbers in parse errors, Add some parser debug aids.
2010-12-15 06:36:47 +01:00
}
Add support for constants and package types. Significant rework of scope management to unify the handling of types in the ieee library and types/constants/components in packages. This involved adjusting the parser rules to manage a stack of scopes and rewriting the IEEE library support to not use global maps for the loaded types.
2011-04-18 02:19:09 +02:00
if (dump_libraries_path) {
ofstream file(dump_libraries_path);
dump_libraries(file);
}
if (dump_design_entities_path) {
ofstream file(dump_design_entities_path);
dump_design_entities(file);
}
Parse create entities with ports Create entity objects from entity declarations in the source, and populate them with ports.
2011-01-03 07:30:09 +01:00
Add parser cleanup to vhdlpp This commit adds removal of global objects in the execution of vhdlpp. This includes deleting design entities and the global parse scope.
2011-07-20 18:19:48 +02:00
if (errors > 0) {
parser_cleanup();
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
return 2;
Add parser cleanup to vhdlpp This commit adds removal of global objects in the execution of vhdlpp. This includes deleting design entities and the global parse scope.
2011-07-20 18:19:48 +02:00
}
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
errors = elaborate_entities();
if (errors > 0) {
fprintf(stderr, "%d errors elaborating design.\n", errors);
Add parser cleanup to vhdlpp This commit adds removal of global objects in the execution of vhdlpp. This includes deleting design entities and the global parse scope.
2011-07-20 18:19:48 +02:00
parser_cleanup();
Emit Verilog stubs for entities The verilog includes the module declaration with correct ports in the correct order. Get the port directions correct.
2011-01-03 08:38:08 +01:00
return 3;
}
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
errors = emit_entities();
if (errors > 0) {
fprintf(stderr, "%d errors emitting design.\n", errors);
Add parser cleanup to vhdlpp This commit adds removal of global objects in the execution of vhdlpp. This includes deleting design entities and the global parse scope.
2011-07-20 18:19:48 +02:00
parser_cleanup();
Code generator for architectures. Separate elaboration from code generation in the Entity, and add to Architectures a code generator to handle some simple cases. At this point we have the basic structure for the VHDL compiler.
2011-01-31 20:16:14 +01:00
return 4;
}
Add parser cleanup to vhdlpp This commit adds removal of global objects in the execution of vhdlpp. This includes deleting design entities and the global parse scope.
2011-07-20 18:19:48 +02:00
parser_cleanup();
Introduce shell of vhdlpp program. Create the makefiles and configuration scripts to hold together the vhdlpp front-end program. Create a shell main.
2010-12-13 05:02:18 +01:00
return 0;
}