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UVM track: seed uvm/, docs, and hello_uvm example Standalone muhammadjawadkhan/iverilog-uvm project setup. Documents that this fork is experimental and must not PR UVM work to steveicarus/iverilog. Seeds uvm/ from IVL_UVM and adds roadmap/status workflow docs plus a smoke example.
2026-07-21 13:14:00 +02:00
# Status
Last updated: 2026-07-21
## Accellera UVM 1.2
**Not supported.** Official Accellera UVM will not compile on stock Icarus or on this fork yet.
## This fork
| Area | Status |
|------|--------|
| Icarus Verilog tree | Fork of `steveicarus/iverilog` (`master` @ merge of SV array ordering work) |
| [`uvm/`](../uvm/) | Seeded from IVL_UVM (VerifWorks) — messaging, CLP, stub phases, poor-man’s mailbox/semaphore; **not** Accellera-compatible |
SV: parse ANSI class parameter port lists Allow class C #(type T = int, ...) so parameterized classes with defaults elaborate; add smoke examples and hello_uvm Makefile.
2026-07-21 13:25:09 +02:00
| [`examples/hello_uvm`](../examples/hello_uvm) | Smoke TB for the seeded library (`Makefile` included) |
SV: add string-keyed associative array vertical slice Support int aa[string]/int aa[*] with assign, size/num, exists, delete, foreach, and whole-array copy for UVM Tier A table patterns. Runtime uses vvp_aarray_vec4 (std::map); int keys and richer element types deferred.
2026-07-21 14:12:16 +02:00
| Parameterized classes | **Partial** on `feat/param-classes` (merged): ANSI `class C #(type T = int, parameter int W = 8);` parses into the class scope and elaborates with **defaults**. Explicit specializations `C#(byte)` / overrides not done yet. See [`examples/param_classes`](../examples/param_classes). |
| Associative arrays | **Partial** on `feat/assoc-array`: string-keyed `int aa[string]` / `int aa[*]` with size/num/exists/delete/foreach/copy. See [`docs/assoc-array.md`](assoc-array.md) and [`examples/assoc_array`](../examples/assoc_array). |
UVM track: seed uvm/, docs, and hello_uvm example Standalone muhammadjawadkhan/iverilog-uvm project setup. Documents that this fork is experimental and must not PR UVM work to steveicarus/iverilog. Seeds uvm/ from IVL_UVM and adds roadmap/status workflow docs plus a smoke example.
2026-07-21 13:14:00 +02:00
| Virtual interfaces | Missing |
| Constraints / randomize | Missing |
| Covergroups / DPI | Missing |
## Remotes
- `origin` → https://github.com/muhammadjawadkhan/iverilog-uvm
- `upstream` → https://github.com/steveicarus/iverilog (fetch only for this track)