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iverilog/parse_api.h

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Update header files to use a more standard name to prevent rereading This is from github report #16. There are likely a few more issues that need to be addressed though this takes care of the major ones.
2014-07-23 22:39:29 +02:00
#ifndef IVL_parse_api_H
#define IVL_parse_api_H
clean up API for restarting parser.
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/*
Elaborate package scopes in textual order (fix for issue #461) When elaborating a subclass, the base class scope needs to be elaborated before the subclass scope. If the base class and subclass are defined in different packages, this requires the package scopes to be elaborated in the correct order. SystemVerilog reqires packages to be defined before they are used, so that is the order we should elaborate them in.
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* Copyright (c) 2001-2021 Stephen Williams (steve@icarus.com)
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*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
updated FSF-address
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
Remove malloc.h support and for C++ files use <c...> include files. The functions (malloc, free, etc.) that used to be provided in malloc.h are now provided in cstdlib for C++ files and stdlib.h for C files. Since we require a C99 compliant compiler it makes sense that malloc.h is no longer needed. This patch also modifies all the C++ files to use the <c...> version of the standard C header files (e.g. <cstdlib> vs <stdlib.h>). Some of the files used the C++ version and others did not. There are still a few other header changes that could be done, but this takes care of much of it.
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# include <cstdio>
Use perm_strings for named langiage items.
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# include "StringHeap.h"
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# include <string>
Import parameters from packages.
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# include <ostream>
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# include <map>
Handle enumeration literals that are in $root.
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# include <set>
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Handle enumeration literals that are in $root.
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class Design;
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class Module;
Classes in $root scope up to elaboration.
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class PClass;
Import parameters from packages.
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class PPackage;
Elaborate root tasks/functions.
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class PTaskFunc;
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class PUdp;
Handle typedefs in $root scope.
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class data_type_t;
Remove lint detected by clang With this change, iverilog builds and runs with no extra warnings when using clang 3.0
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struct enum_type_t;
clean up API for restarting parser.
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/*
* These are maps of the modules and primitives parsed from the
* Verilog source into pform for elaboration. The parser adds modules
Spelling fixes only comments and documentation some punctuation and capitalization for good measure Changelogs are purposefully untouched
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* to these maps as it compiles modules in the Verilog source.
clean up API for restarting parser.
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*/
Import parameters from packages.
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extern std::map<perm_string,Module*> pform_modules;
extern std::map<perm_string,PUdp*> pform_primitives;
Support separate compilation units in SystemVerilog. The compilation unit scope is now treated as a specialised form of package (with an automatically generated name). All items declared outside a design element are added to the current compilation unit package. Apart from when searching for a symbol, once we get into elaboration we can treat these just like any other package.
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extern std::vector<PPackage*> pform_units;
Elaborate package scopes in textual order (fix for issue #461) When elaborating a subclass, the base class scope needs to be elaborated before the subclass scope. If the base class and subclass are defined in different packages, this requires the package scopes to be elaborated in the correct order. SystemVerilog reqires packages to be defined before they are used, so that is the order we should elaborate them in.
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extern std::vector<PPackage*> pform_packages;
Classes in $root scope up to elaboration.
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Elaborate root tasks/functions.
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extern void pform_dump(std::ostream&out, const PClass*pac);
Import parameters from packages.
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extern void pform_dump(std::ostream&out, const PPackage*pac);
Elaborate root tasks/functions.
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extern void pform_dump(std::ostream&out, const PTaskFunc*tf);
clean up API for restarting parser.
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/*
First step towards supporting separate compilation units in SV. This adds a -u option to the driver to allow the user to specify that they want each source file to be treated as a separate compilation unit, and modifies the compiler to accept a list of files (either on the command line or via a file specified by a new -F option). This list of files is then preprocessed and parsed separately, causing all compiler directives (including macro definitions) to only apply to the file containing them, as required by the SystemVerilog standard.
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* This code actually invokes the parser to make modules. If the path
* parameter is "-", the parser reads from stdin, otherwise it attempts
* to open and read the specified file. When reading from a file, if
* the ivlpp_string variable is not set to null, the file will be piped
* through the command specified by ivlpp_string before being parsed.
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*/
First step towards supporting separate compilation units in SV. This adds a -u option to the driver to allow the user to specify that they want each source file to be treated as a separate compilation unit, and modifies the compiler to accept a list of files (either on the command line or via a file specified by a new -F option). This list of files is then preprocessed and parsed separately, causing all compiler directives (including macro definitions) to only apply to the file containing them, as required by the SystemVerilog standard.
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extern int pform_parse(const char*path);
clean up API for restarting parser.
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Handle implicit task/function imports in the unit scope SystemVerilog requires that functions and tasks are not implicitly imported if a symbol with the same name appears in the scope, even if it the symbol is declared after its usage. To support this a list of potential imports is collected while parsing a scope and only when the end of the scope is reached it is evaluated whether the symbol should be imported or not based on whether it already exists in the scope. This currently works fine for all scopes except for the unit scope. Since the unit scope might span multiple files it is never explicitly closed and the potential imports are never checked. Make sure that after parsing all files is done the potential imports for the unit scope are checked. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2023-06-03 03:58:42 +02:00
extern void pform_finish();
Remove "using namespace std" from compiler header files and fix the fallout.
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extern std::string vl_file;
clean up API for restarting parser.
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Add support for `resetall and other directive changes. This patch adds support for the `resetall directive. It also changes `celldefine, `endcelldefine and `resetall to no longer grab text following them. These directives do not take an argument so they should not be grabbing any text and silently discarding it. The `timescale processing was reworked to handle being reset and hooks were added to easily change the default time units and precision when we add that feature request.
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extern void pform_set_timescale(int units, int prec, const char*file,
unsigned lineno);
extern int def_ts_units;
extern int def_ts_prec;
Update header files to use a more standard name to prevent rereading This is from github report #16. There are likely a few more issues that need to be addressed though this takes care of the major ones.
2014-07-23 22:39:29 +02:00
#endif /* IVL_parse_api_H */