88 lines
2.3 KiB
C++
88 lines
2.3 KiB
C++
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/*
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* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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# include "entity.h"
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# include "architec.h"
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# include <iostream>
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# include <fstream>
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# include <iomanip>
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int emit_entities(void)
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{
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int errors = 0;
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for (map<perm_string,Entity*>::iterator cur = design_entities.begin()
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; cur != design_entities.end() ; ++cur) {
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errors += cur->second->emit(cout);
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}
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return errors;
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}
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int Entity::emit(ostream&out)
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{
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int errors = 0;
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out << "module " << name_;
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// If there are ports, emit them.
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if (ports.size() > 0) {
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out << "(";
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const char*sep = 0;
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for (vector<InterfacePort*>::iterator cur = ports.begin()
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; cur != ports.end() ; ++cur) {
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InterfacePort*port = *cur;
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// FIXME: this is a stub. This port handling code
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// currently only supports std_logic signal tyes,
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// so just assert that the user asked for std_logic.
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if (port->type_name != "std_logic") {
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cerr << "sorry: VHDL only supports std_logic ports."
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<< " Expecting std_logic, but got \""
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<< port->type_name << "\"" << endl;
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errors += 1;
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}
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if (sep) out << sep;
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else sep = ", ";
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switch (port->mode) {
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case PORT_NONE: // Should not happen
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out << "NO_PORT " << port->name;
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break;
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case PORT_IN:
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out << "input " << port->name;
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break;
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case PORT_OUT:
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out << "output " << port->name;
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break;
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}
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}
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cout << ")";
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}
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out << ";" << endl;
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errors += bind_arch_->emit(out, this);
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out << "endmodule" << endl;
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return errors;
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}
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