31 lines
815 B
Systemverilog
31 lines
815 B
Systemverilog
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// Clocking-block vertical slice (UVM Tier A #4).
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// Interface-local clocking with @(bif.cb), NBA write, and sampled read.
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interface bus_if(input logic clk);
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logic [7:0] data;
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logic req;
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clocking cb @(posedge clk);
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input #0 data;
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output #0 req;
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endclocking
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endinterface
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module top;
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logic clk;
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bus_if bif(clk);
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logic [7:0] x;
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initial begin clk = 0; forever #5 clk = ~clk; end
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initial begin
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bif.data = 8'h3C;
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@(bif.cb);
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bif.cb.req <= 1'b1; // NBA to underlying req (#0 skew)
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x = bif.cb.data; // #0 sample of data
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@(bif.cb); // next clocking event: NBA is visible on bif.req
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if (x !== 8'h3C || bif.req !== 1'b1) begin
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$display("FAILED x=%0h req=%0b", x, bif.req);
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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