iverilog/examples/clocking
mjoekhan 9601928032 SV: add interface clocking-block vertical slice for UVM
Parse interface-local clocking blocks, treat cb as a transparent hop for
member R/W, and elaborate @(bif.cb) as the clocking event so basic driver
sync works with #0 skew.
2026-07-21 18:16:16 +05:00
..
cb_basic.sv SV: add interface clocking-block vertical slice for UVM 2026-07-21 18:16:16 +05:00