luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
iverilog/docs/STATUS.md

28 lines
2.2 KiB
Markdown
Raw Normal View History

UVM track: seed uvm/, docs, and hello_uvm example Standalone muhammadjawadkhan/iverilog-uvm project setup. Documents that this fork is experimental and must not PR UVM work to steveicarus/iverilog. Seeds uvm/ from IVL_UVM and adds roadmap/status workflow docs plus a smoke example.
2026-07-21 13:14:00 +02:00
# Status
Last updated: 2026-07-21
## Accellera UVM 1.2
**Not supported.** Official Accellera UVM will not compile on stock Icarus or on this fork yet.
## This fork
| Area | Status |
|------|--------|
| Icarus Verilog tree | Fork of `steveicarus/iverilog` (`master` @ merge of SV array ordering work) |
SV: add mailbox/semaphore builtins for UVM IPC Implement native SystemVerilog mailbox and semaphore with blocking and nonblocking put/get, so Accellera-style code can use the standard API without depending on the legacy IVL_UVM poor-man's classes.
2026-07-21 15:37:08 +02:00
| [`uvm/`](../uvm/) | Seeded from IVL_UVM (VerifWorks) — messaging, CLP, stub phases, legacy poor-man’s mailbox/semaphore classes; **not** Accellera-compatible. Prefer compiler builtins for `mailbox`/`semaphore` (see STATUS row below). |
SV: parse ANSI class parameter port lists Allow class C #(type T = int, ...) so parameterized classes with defaults elaborate; add smoke examples and hello_uvm Makefile.
2026-07-21 13:25:09 +02:00
| [`examples/hello_uvm`](../examples/hello_uvm) | Smoke TB for the seeded library (`Makefile` included) |
SV: add string-keyed associative array vertical slice Support int aa[string]/int aa[*] with assign, size/num, exists, delete, foreach, and whole-array copy for UVM Tier A table patterns. Runtime uses vvp_aarray_vec4 (std::map); int keys and richer element types deferred.
2026-07-21 14:12:16 +02:00
| Parameterized classes | **Partial** on `feat/param-classes` (merged): ANSI `class C #(type T = int, parameter int W = 8);` parses into the class scope and elaborates with **defaults**. Explicit specializations `C#(byte)` / overrides not done yet. See [`examples/param_classes`](../examples/param_classes). |
| Associative arrays | **Partial** on `feat/assoc-array`: string-keyed `int aa[string]` / `int aa[*]` with size/num/exists/delete/foreach/copy. See [`docs/assoc-array.md`](assoc-array.md) and [`examples/assoc_array`](../examples/assoc_array). |
SV: add virtual-interface vertical slice for UVM agents Support virtual interface class properties/TF args, instance bind, member R/W, and @(posedge vif.clk) so basic driver connectivity works.
2026-07-21 14:58:35 +02:00
| Virtual interfaces | **Partial** on `feat/virtual-interface`: `virtual interface T` as class property / TF arg; assign interface instance; member R/W; `@(posedge vif.clk)`. See [`docs/virtual-interface.md`](virtual-interface.md) and [`examples/virtual_interface`](../examples/virtual_interface). |
SV: add interface clocking-block vertical slice for UVM Parse interface-local clocking blocks, treat cb as a transparent hop for member R/W, and elaborate @(bif.cb) as the clocking event so basic driver sync works with #0 skew.
2026-07-21 15:16:16 +02:00
| Clocking blocks | **Partial** on `feat/clocking-blocks`: interface-local `clocking`; `@(bif.cb)`; `cb.sig` R/W with `#0` skew. See [`docs/clocking.md`](clocking.md) and [`examples/clocking`](../examples/clocking). |
SV: add mailbox/semaphore builtins for UVM IPC Implement native SystemVerilog mailbox and semaphore with blocking and nonblocking put/get, so Accellera-style code can use the standard API without depending on the legacy IVL_UVM poor-man's classes.
2026-07-21 15:37:08 +02:00
| Mailbox / semaphore | **Partial** on `feat/mailbox-semaphore`: compiler builtins; `mailbox #(int)` + blocking/nonblocking put/get/num; `semaphore` get/put/try_get. See [`docs/mailbox-semaphore.md`](mailbox-semaphore.md) and [`examples/mailbox_sem`](../examples/mailbox_sem). |
UVM track: seed uvm/, docs, and hello_uvm example Standalone muhammadjawadkhan/iverilog-uvm project setup. Documents that this fork is experimental and must not PR UVM work to steveicarus/iverilog. Seeds uvm/ from IVL_UVM and adds roadmap/status workflow docs plus a smoke example.
2026-07-21 13:14:00 +02:00
| Constraints / randomize | Missing |
| Covergroups / DPI | Missing |
## Remotes
- `origin` → https://github.com/muhammadjawadkhan/iverilog-uvm
- `upstream` → https://github.com/steveicarus/iverilog (fetch only for this track)