iverilog/net_nex_output.cc

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/*
* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: net_nex_output.cc,v 1.1 2002/06/30 02:21:32 steve Exp $"
#endif
#if !defined(WINNT)
#ident "$Id: net_nex_output.cc,v 1.1 2002/06/30 02:21:32 steve Exp $"
#endif
# include "config.h"
# include <iostream>
# include <cassert>
# include <typeinfo>
# include "netlist.h"
# include "netmisc.h"
void NetProc::nex_output(NexusSet&out)
{
cerr << get_line()
<< ": internal error: NetProc::nex_output not implemented"
<< endl;
}
void NetAssign::nex_output(NexusSet&out)
{
cerr << get_line()
<< ": internal error: NetProc::nex_output not implemented"
<< endl;
}
void NetCondit::nex_output(NexusSet&out)
{
cerr << get_line()
<< ": internal error: NetProc::nex_output not implemented"
<< endl;
}
/*
* $Log: net_nex_output.cc,v $
* Revision 1.1 2002/06/30 02:21:32 steve
* Add structure for asynchronous logic synthesis.
*
*/