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iverilog/vhdlpp/vsignal.cc

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Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
/*
* Copyright (c) 2011 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "vsignal.h"
VHDL initialization expressions for signals.
2011-10-30 02:06:40 +02:00
# include "expression.h"
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
# include "vtype.h"
# include <iostream>
using namespace std;
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
VHDL initialization expressions for signals.
2011-10-30 02:06:40 +02:00
SigVarBase::SigVarBase(perm_string nam, const VType*typ, Expression*exp)
: name_(nam), type_(typ), init_expr_(exp), refcnt_sequ_(0)
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
{
}
Handle variables in process statements Parse variables declared in the declaration section of process statements, and support variable assignment statements.
2011-08-18 05:19:15 +02:00
SigVarBase::~SigVarBase()
Parse component declarations / parse signal declarations. These go into the architecture/block of their scope and will be used by component instantiations to make sure the bindings are correct and complete. Also handle signal declarations. The elaborator will use these to generate module local variables that are used by the architecture.
2011-03-22 17:16:20 +01:00
{
}
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
Handle variables in process statements Parse variables declared in the declaration section of process statements, and support variable assignment statements.
2011-08-18 05:19:15 +02:00
void SigVarBase::type_elaborate_(VType::decl_t&decl)
{
Rework elaborate/emit of types. This rework is needed to reasonably handle new types, like enums.
2011-10-02 19:56:00 +02:00
decl.type = type_;
Handle variables in process statements Parse variables declared in the declaration section of process statements, and support variable assignment statements.
2011-08-18 05:19:15 +02:00
}
VHDL initialization expressions for signals.
2011-10-30 02:06:40 +02:00
int Signal::emit(ostream&out, Entity*ent, Architecture*arc)
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
{
int errors = 0;
VType::decl_t decl;
Handle variables in process statements Parse variables declared in the declaration section of process statements, and support variable assignment statements.
2011-08-18 05:19:15 +02:00
type_elaborate_(decl);
if (peek_refcnt_sequ_() > 0)
decl.reg_flag = true;
errors += decl.emit(out, peek_name_());
VHDL initialization expressions for signals.
2011-10-30 02:06:40 +02:00
Expression*init_expr = peek_init_expr();
if (init_expr) {
out << " = ";
init_expr->emit(out, ent, arc);
}
Handle variables in process statements Parse variables declared in the declaration section of process statements, and support variable assignment statements.
2011-08-18 05:19:15 +02:00
out << ";" << endl;
return errors;
}
int Variable::emit(ostream&out, Entity*, Architecture*)
{
int errors = 0;
VType::decl_t decl;
type_elaborate_(decl);
if (peek_refcnt_sequ_() > 0)
vhdl sequential l-values cause variables to be reg vs. net. When a signal (or port) is assigned by a sequential assignment, the signal or port becomes a reg, instead of a wire(net). Detect this distinction during elaboration and generate the correct signal/port declaration.
2011-06-13 00:38:03 +02:00
decl.reg_flag = true;
Handle variables in process statements Parse variables declared in the declaration section of process statements, and support variable assignment statements.
2011-08-18 05:19:15 +02:00
errors += decl.emit(out, peek_name_());
Declare vhdl module ports inline, a la ansi-c Keep the entity/component/module port declarations in the module port list of the generated code. This clarifies the generated code and fixes a couple bugs for more complicated types.
2011-06-03 04:11:20 +02:00
out << ";" << endl;
Add more complete support for vhdl local signals. These signals are declared in the architecture and are local to the module. The Architecture already parsed and stored these signal declarations, but this patch adds the ability to actually emit these signals in the generated code. In the process of doing this, I had to regularize the elaboration and emit of VTypes, so that it can be used in multiple places, not just in entity headers (for ports). I also added support for bit selects of signals. This effected a couple places in the parser, and expressions in general.
2011-03-27 21:01:58 +02:00
return errors;
}